Circuitized substrate with filled isolation border, method of making same, electrical assembly utilizing same, and information handling system utilizing same
View Patent ↗A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
1. A circuitized substrate comprising:
at least one electrically conductive layer of substantially planar configuration and having first and second opposing surfaces, said at least one electrically conductive layer including at least one side edge portion comprised of a plurality of contiguous formed open segments;
a first dielectric layer positioned on said first opposing surface of said at least one electrically conductive layer, a portion of said first dielectric layer being positioned within selected ones of said contiguous formed open segments of said at least one side edge portion, said first dielectric layer including a plurality of openings each aligned above a respective one of the remaining ones of said contiguous formed open segments; and
a second dielectric layer positioned on said second opposing surface of said at least one electrically conductive layer, a portion of said second dielectric layer being positioned within said remaining ones of said contiguous formed open segments of said at least one side edge portion and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, only said portion of said first dielectric layer being positioned within said selected ones of said contiguous formed open segments of said at least one side edge portion and substantially only said portion of said second dielectric layer being positioned with said remaining ones of said contiguous formed open segments of said at least one side edge portion and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, said portions of both of said first and second dielectric layers being positioned within said contiguous formed open segments of said at least one side edge portion providing a substantially solid dielectric covering over said plurality of said continuous formed open segments of said at least one side edge portion.
2. The circuitized substrate of claim 1 wherein said plurality of contiguous formed open segments are drilled partial openings.
3. The circuitized substrate of claim 1 wherein said at least one electrically conductive layer is comprised of copper.
4. The circuitized substrate of claim 1 wherein said first dielectric layer comprises a resin material as part thereof.
5. The circuitized substrate of claim 4 wherein said first dielectric layer further comprises reinforcement material.
6. The circuitized substrate of claim 5 wherein said reinforcement material comprises fiberglass.
7. The circuitized substrate of claim 1 wherein said second dielectric layer comprises a resin material as part thereof.
8. The circuitized substrate of claim 7 wherein said second dielectric layer further comprises reinforcement material.
9. The circuitized substrate of claim 8 wherein said reinforcement material comprises fiberglass.
10. An electrical assembly comprising:
a circuitized substrate including at least one electrically conductive layer of substantially planar configuration and having first and second opposing surfaces, said at least one electrically conductive layer including at least one side edge portion comprised of a plurality of contiguous formed open segments, a first dielectric layer positioned on said first opposing surface of said at least one electrically conductive layer, a portion of said first dielectric layer being positioned within selected ones of said contiguous formed open segments of said at least one side edge portion, said first dielectric layer including a plurality of openings each aligned above a respective one of the remaining ones of said contiguous formed open segments, and a second dielectric layer positioned on said second opposing surface of said at least one electrically conductive layer, a portion of said second dielectric layer being positioned within said remaining ones of said contiguous formed open segments of said at least one side edge portion and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, only said portion of said first dielectric layer being positioned within said selected ones of said contiguous formed open segments of said at least one side edge portion and substantially only said portion of said second dielectric layer being positioned with said remaining ones of said contiguous formed open segments of said at least one side edge portion and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, said portions of both of said first and second dielectric layers being positioned within said contiguous formed open segments of said at least one side edge portion providing a substantially solid dielectric covering over said plurality of said continuous formed open segments of said at least one side edge portion; and
at least one electrical component positioned on and electrically coupled to said circuitized substrate.
11. The electrical assembly of claim 10 wherein said plurality of contiguous formed open segments are drilled partial openings.
12. The electrical assembly of claim 10 wherein said at least one electrically conductive layer is comprised of copper.
13. The electrical assembly of claim 10 wherein said first dielectric layer comprises a resin material as part thereof.
14. The electrical assembly of claim 13 wherein said first dielectric layer further comprises reinforcement material.
15. The electrical assembly of claim 14 wherein said reinforcement material comprises fiberglass.
16. The electrical assembly of claim 10 wherein said second dielectric layer comprises a resin material as part thereof.
17. The electrical assembly of claim 16 wherein said second dielectric layer further comprises reinforcement material.
18. The electrical assembly of claim 17 wherein said reinforcement material comprises fiberglass.
19. The electrical assembly of claim 10 wherein said at least one electrical component positioned on and electrically coupled to said circuitized substrate comprises a chip carrier.
20. The electrical assembly of claim 10 wherein said at least one electrical component positioned on and electrically coupled to said circuitized substrate comprises a semiconductor chip.
21. A multilayered circuitized structure comprising:
a first circuitized substrate portion including at least one electrically conductive layer of substantially planar configuration and having first and second opposing surfaces, said at least one electrically conductive layer including at least one side edge portion comprised of a plurality of contiguous formed open segments, a first dielectric layer positioned on said first opposing surface of said at least one electrically conductive layer, a portion of said first dielectric layer being positioned within selected ones of said contiguous formed open segments of said at least one side edge portion, said first dielectric layer including a plurality of openings each aligned above a respective one of the remaining ones of said contiguous formed open segments, and a second dielectric layer positioned on said second opposing surface of said at least one electrically conductive layer, a portion of said second dielectric layer being positioned within said remaining ones of said contiguous formed open segments of said at least one side edge portion and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, only said portion of said first dielectric layer being positioned within said selected ones of said contiguous formed open segments of said at least one side edge portion and substantially only said portion of said second dielectric layer being positioned with said remaining ones of said contiguous formed open segments of said at least one side edge portion and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, said portions of both of said first and second dielectric layers being positioned within said contiguous formed open segments of said at least one side edge portion providing a substantially solid dielectric covering over said plurality of said continuous formed open segments of said at least one side edge portion, said circuitized substrate having a first pattern of interconnecting thru-holes therein of a first density; and
second and third circuitized substrate portions positioned on opposite sides of said first circuitized substrate portion, each having a second pattern of interconnecting thru-holes therein, said second patterns of interconnecting thru-holes being electrically coupled to said interconnecting conductive thru-holes of said first circuitized substrate portion such that said first circuitized substrate portion provides electrical interconnection between said second and third circuitized substrate portions.
22. The invention of claim 21 wherein said multilayered circuitized structure is a printed circuit board.
23. The invention of claim 21 wherein said multilayered circuitized structure is a chip carrier.
24. The invention of claim 21 further including at least one semiconductor chip positioned on or within said chip carrier and forming part thereof.