IP Library Granted Patent US 7,211,289
Granted Patent B2
US 7,211,289 · App. 10/737,974 · Granted May 1, 2007

Method of making multilayered printed circuit board with filled conductive holes

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Quick Facts
Patent No.
US 7,211,289
App. No.
10/737,974
Granted
May 1, 2007
Kind
B2
Abstract

A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

Claims (28)

1. A method of making a multilayered printed circuit board, said method comprising:

providing a first dielectric layer having first and second opposing sides;

forming a first conductive layer on said first opposing side of said first dielectric layer;

forming a second conductive layer on said second opposing side of said first dielectric layer, said second conductive layer including at least one opening therein;

forming a second dielectric layer having first and second opposing sides on said second conductive layer on said second opposing side of said first dielectric layer, said first opposing side of said second dielectric layer being in contact with at least part of said second conductive layer including over said at least one opening therein;

forming first and second holes within said second dielectric layer using a laser, said first hole extending down to only said second conductive layer and a part of said second hole extending through said at least one opening in said second conductive layer and down to said first conductive layer, said first and second holes, including said part of said second hole extending through said at least one opening in said second conductive layer and down to said first conductive layer, each being of tapered configuration and having surfaces;

forming a third conductive layer on said second opposing side of said second dielectric layer;

forming a conductive coating on said surfaces of said first and second holes so as to electrically couple said first and second conductive layers with said conductive coating on said second hole and said second and third conductive layers with said conductive coating on said first hole;

plating said first and second holes having said conductive coatings thereon with plating material to fill said first and second holes, including said part of said second hole extending through said at least one opening in said second conductive layer and down to said first conductive layer; and

forming a substantially solid upper surface on said conductive material within each of said first and second holes.

2. The method of claim 1 wherein said conductive coating on said second hole also electrically couples said second conductive layer and said third conductive layer.

3. The method of claim 1 wherein said first, second and third conductive layers are formed using photolithographic processing.

4. The method of claim 1 wherein said conductive coatings are formed on said surfaces of each of said holes using a plating process.

5. The method of claim 1 wherein said second dielectric layer is formed on said second conductive layer using a laminating process.

6. A method of making a multilayered printed circuit board, said method comprising:

providing a first dielectric layer having first and second opposing sides;

forming a first conductive layer on said first opposing side of said first dielectric layer;

forming a second conductive layer on said second opposing side of said first dielectric layer, said second conductive layer including at least one opening therein;

forming a second dielectric layer having first and second opposing sides on said second conductive layer on said second opposing side of said first dielectric layer, said first opposing side of said second dielectric layer being in contact with at least part of said second conductive layer including over said at least one opening therein;

forming first and second holes within said second dielectric layer using a laser, said first hole extending down to only said second conductive layer and a part of said second hole extending through said at least one opening in said second conductive layer and down to said first conductive layer, said first and second holes, including said part of said second hole extending through said at least one opening in said second conductive layer and down to said first conductive layer, each being of tapered configuration and having surfaces;

forming a third conductive layer on said second opposing side of said second dielectric layer;

forming a conductive coating on said surfaces of said first and second holes so as to electrically couple said first and second conductive layers with said conductive coating on said second hole and said second and third conductive layers with said conductive coating on said first hole;

filling said first and second holes having said conductive coatings thereon with conductive paste, including said part of said second hole extending through said at least one opening in said second conductive layer and down to said first conductive layer; and

forming a conductive layer over said conductive paste within each of said first and second holes.

7. The method of claim 6 wherein said conductive coating on said second hole also electrically couples said second conductive layer and said third conductive layer.

8. The method of claim 6 wherein said first, second and third conductive layers are formed using photolithographic processing.

9. The method of claim 6 wherein said conductive coatings are formed on said surfaces of each of said holes using a plating process.

10. The method of claim 6 wherein said second dielectric layer is formed on said second conductive layer using a laminating process.

Assignments (17)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2008
From: WACHOVIA CAPITAL FINANCE CORPORATION
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 021861/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2007
From: WACHOVIA BANK, NATIONAL ASSOCIATION, AS AGENT
To: WACHOVIA CAPITAL FINANCE CORPORATION ( NEW ENGLAND), AS AGENT
Reel/Frame 019304/0676 →
SECURITY AGREEMENT Recorded May 10, 2005
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: WACHOVIA BANK, NATIONAL ASSOCIATION, AS AGENT
Reel/Frame 016561/0605 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2003
From: LARNERD, JAMES M.; LAUFFER, JOHN M.; MARKOVICH, VOYA R.; PAPATHOMAS, KOSTAS I.
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 014818/0367 →