Method of making a circuitized substrate with enhanced circuitry and electrical assembly utilizing said substrate
View Patent ↗A method of making a circuitized substrate in which pairs of vertically oriented though holes are formed such that at least one of the through holes is partially embedded within a lower one, thus assuring a sound connection following subsequent lamination or other steps the substrate including such holes is subjected to during manufacture. An electrical assembly including a substrate with such features is also provided.
1. A method of making a circuitized substrate, said method comprising:
providing a first layer of dielectric material;
forming a first conductive through-hole within said first layer of dielectric material, said first conductive through-hole including a land portion and a barrel portion;
applying a second layer of dielectric material over said first conductive through-hole including said land portion such that a portion of said dielectric material of said second layer will substantially fill said first conductive through-hole;
removing a part of said dielectric material of said second layer from above said land portion and from a predetermined depth within said first conductive through-hole, said removing resulting in the formation of internal walls of said dielectric material of said second layer having a predefined configuration and an upper surface of said dielectric material of said second layer at said predetermined level within said first conductive through hole; and
plating metallurgy on said internal walls of said dielectric material of said second layer, on the internal walls of said first conductive through-hole to substantially said predetermined depth within said first conductive through hole, and on said upper surface of said dielectric material of said second layer, to form a second conductive through-hole electrically coupled to and partially positioned within said first conductive through-hole within said first layer of dielectric material.
2. The method of claim 1 wherein said predefined configuration of said internal walls of said dielectric material of said second layer is tapered.
3. The method of claim 1 wherein said forming of said first conductive through-hole within said first layer of dielectric material including said land portion and said barrel portion is accomplished using an electroplating operation.
4. The method of claim 3 wherein said electroplating operation includes a first electro-less plating step and a second electrolytic plating step.
5. The method of claim 4 wherein said first electro-less plating step provides a thin layer of metal and said second electrolytic plating step provides a second, thicker layer of metal on said thin layer.
6. The method of claim 1 wherein said applying said second layer of dielectric material over said first conductive through-hole including said land portion such that a portion of said dielectric material of said second layer will substantially fill said barrel portion of said first conductive through-hole is accomplished using lamination.
7. The method of claim 1 wherein said removing said part of said dielectric material of said second layer from above said land portion and from a predetermined depth within said first conductive through-hole is accomplished using laser ablation.
8. The method of claim 1 wherein said plating of said metallurgy on said internal walls of said dielectric material of said second layer, on said internal walls of said first conductive through-hole to substantially said predetermined depth within said first conductive through hole, and on said upper surface of said dielectric material of said second layer, to form said second conductive through-hole electrically coupled to said conductive through-hole within said first layer of dielectric material is accomplished using an electroplating operation.
9. The method of claim 8 wherein said electroplating operation includes a first electro-less plating step and a second electrolytic plating step.
10. The method of claim 9 wherein said first electro-less plating step provides a thin layer of metal and said second electrolytic plating step provides a second, thicker layer of metal on said thin layer.
11. The method of claim 1 further including electrically coupling an electrical component to said second electrically conductive through hole, said circuitized substrate and said electronic component comprising an electrical assembly.
12. The method of claim 11 wherein said electrical component is a semiconductor chip, said electrically coupling of said semiconductor chip to said second electrically conductive through-hole being accomplished utilizing a plurality of solder elements.
13. The method of claim 11 further including electrically coupling said circuitized substrate to a second circuitized substrate.
14. The method of claim 13 wherein said second circuitized substrate is a printed circuit board, said electrically coupling of said circuitized substrate to said second circuitized substrate being accomplished utilizing a plurality of solder elements.
15. The method of claim 13 further including providing a housing and thereafter positioning said electrical assembly within said housing, said housing and said electrical assembly comprising an information handling system.
16. The method of claim 11 further including filling said second conductive through-hole with conductive material.
17. An electrical assembly comprising: a circuitized substrate including a first layer of dielectric material, a first plated through hole within said first layer of dielectric material and including a land portion and a barrel portion, a second layer of dielectric material positioned on said first layer of dielectric material and substantially filled said first plated through hole, and a second plated through hole within said second layer of dielectric material, said second plated though hole extending a predetermined depth within said first plated through hole; and an electrical component positioned on said circuitized substrate and electrically coupled to said second plated through hole.
18. The electrical assembly of claim 17 wherein said dielectric material of said first and second layers is selected from the group consisting of fiberglass-reinforced epoxy resin, polytetrafluoroethylene, polyimide, polyamide, cyanate resin, photo-imageable material, and combinations thereof.
19. The electrical assembly of claim 17 wherein said first and second plated through holes include at least one layer of copper or copper alloy on the internal walls thereof, part of said layer of copper or copper alloy of said second plated through hole also being located on part of said layer of copper or copper alloy substantially within said land portion of said first plated through hole.
20. The electrical assembly of claim 17 wherein said part of said layer of copper or copper alloy of said second plated through hole which is also located on said part of said layer of copper or copper alloy substantially within said land portion of said first plated through hole extends a distance of from about seven to about fourteen percent of the entire depth of said first plated through hole.
21. The electrical assembly of claim 17 wherein said electrical component is a semiconductor chip and said circuitized substrate is a chip carrier.
22. The electrical assembly of claim 17 wherein said electrical component is a chip carrier and said circuitized substrate is a printed circuit board.