Wideband termination for high power applications

1. A wideband termination circuit layout for high power applications, the circuit comprising:

a dielectric layer having a first surface and a second surface;

at least two resistive film patches disposed over the first surface of the dielectric layer; and

a tuning line between the at least two resistive films disposed over the first surface of the dielectric layer, wherein the at least two resistive film patches are connected in series with the at least one tuning line, wherein the at least two resistive film patches have a first end connected to a first ground and a second ground, respectively.

2. The circuit layout of claim 1 ,

wherein a first patch of the at least two resistive film patches has a second end connected to an input port disposed over the first surface,

wherein the input port is connected to a first end of the at least one tuning line,

wherein a second patch of the at least two resistive film patches has a second end connected with a second end of the at least one tuning line.

3. The circuit layout of claim 1 ,

wherein the input port and the second ground are conductive strips disposed over a first portion and a second portion of a first edge of the dielectric layer,

wherein the first ground is a conductive strip disposed over a second edge of the dielectric layer,

wherein the second edge is opposite to the first edge,

wherein the input port is opposite to the first ground.

4. The circuit layout of claim 2 , wherein the wideband termination circuit layout has a bandwidth at a return loss of 25 dB from DC to 7.0 GHz at the RF frequency F 0 of 6.0 GHz.

5. The circuit layout of claim 2 ,

wherein the at least one tuning line has an inductance of 2.56 nH,

wherein the first and second patches of the at least two resistive film patches have a resistance of 100 ohms,

wherein the first and second patches of the at least two resistive film patches associated with a respective first and second parasitic capacitors have a capacitance of 0.2 pF.

6. The circuit layout of claim 1 , wherein the at least two resistive film patches comprise four resistive film patches disposed over the first surface of the dielectric layer.

7. The circuit layout of claim 6 , wherein the at least one tuning line is connected to each of the four resistive film patches.

8. The circuit layout of claim 7 , wherein the at least one tuning line is arranged substantially parallel to a first edge of the dielectric layer, wherein the input port is positioned near a center of the first edge, and connected to the at least one tuning line.

9. The circuit layout of claim 8 , wherein each of the four resistive film patches has a ground or a plated edge including at least one connection via substantially perpendicular to the first edge.

10. The circuit layout of claim 1 , wherein the at least two resistive film patches comprise three resistive film patches disposed over the first surface of the dielectric layer.

11. The circuit layout of claim 10 ,

wherein a first patch of the three resistive film patches is disposed in the middle of the first surface of the dielectric layer,

wherein the first patch of the three resistive film patches has a first end connecting to the input port and a second end connecting to a first ground,

wherein the first ground is a conductive strip disposed over a first edge of the dielectric layer.

12. The circuit layout of claim 11 ,

wherein a second patch and a third patch of the three resistive film patches are disposed on each side of the first of the three resistive film patches,

wherein each of the second and third patches of the three resistive film patches is connected to a respective second ground and a third ground,

wherein the second ground and the third ground are conductive strips disposed over a second edge of the dielectric layer, wherein the second edge is opposite to the first edge.

13. The circuit layout of claim 12 ,

wherein the at least one tuning line comprises a first tuning line and a second tuning line in parallel with the first tuning line,

wherein the second patch of the three resistive film patches is connected to the first tuning line,

wherein the third patch of the three resistive film patches is connected to the second tuning line.

14. The circuit layout of claim 13 , wherein the input port is connected to the first tuning line and the second tuning line, wherein the input port is disposed over a center of the second edge between the second and third grounds.

15. A termination device comprising the circuit layout of claim 1 and a heat sink attached to the second surface of the dielectric layer.

16. A wideband termination circuit for high power applications, the circuit comprising:

a first termination resistor having a first end and a second end;

a second termination resistor having a first end and a second end;

a Pi impedance network or C-L-C network equivalent to an equivalent transmission line with a characteristic impedance Z TL , and an electric length l,

wherein the equivalent transmission line is connected between the first end of first termination resistor and the first end of the second termination resistor,

wherein the equivalent transmission line is connected to the input port,

wherein the characteristic impedance Z TL is equal to the resistance of the second termination resistor at an RF frequency F 0 .

17. The circuit of claim 16 , wherein the Pi impedance network comprises a first capacitor and a second capacitor, and an inductor connected between the first and second capacitors in series.

18. The circuit of claim 17 , wherein the wideband termination circuit has a bandwidth at a return loss of 25 dB from DC to 7.0 GHz at the RF frequency F 0 of 6.0 GHz.

19. The circuit of claim 16 , wherein the first end of the first termination resistor connects to an input port, the second end of the first termination resistor connects to a first ground, the second end of the second termination resistor connects to a second ground.