IP Library Granted Patent US 7,209,368
Granted Patent B2
US 7,209,368 · App. 10/790,747 · Granted Apr 24, 2007

Circuitized substrate with signal wire shielding, electrical assembly utilizing same and method of making

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Quick Facts
Patent No.
US 7,209,368
App. No.
10/790,747
Granted
Apr 24, 2007
Kind
B2
Abstract

A circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.

Claims (24)

1. A circuitized substrate comprising:

first and second dielectric layers, each of said first and second dielectric layers having first and second opposing sides;

a substantially solid conductive ground plane located between said first opposing side of said first dielectric layer and said first opposing side of said second dielectric layer;

a first conductive signal line located on said second opposing side of said first dielectric layer and a second conductive line located on said second opposing side of said second dielectric layer;

first and second conductive ground lines located on said second opposing side of said first dielectric layer on opposite sides of said first conductive signal line and electrically coupled to said substantially solid conductive ground plane located on said first opposing side of said dielectric layer; and

a first conductive thru-hole extending through said substantially solid conductive ground plane and electrically coupling said first conductive signal line to said second conductive signal line, said first and second conductive ground lines and said substantially conductive ground plane providing shielding for said at least one conductive signal line during the passage of electrical current through said signal line.

2. The circuitized substrate of claim 1 wherein said first and second dielectric layers are each selected from the group consisting of fiberglass-reinforced polymer resin, Teflon and Driclad and combinations thereof.

3. The circuitized substrate of claim 1 wherein said substantially solid conductive ground plane is comprised of copper.

4. The circuitized substrate of claim 1 wherein each of said first and second conductive signal lines is comprised of copper.

5. The circuitized substrate of claim 1 wherein said first and second conductive ground lines are each comprised of copper.

6. The circuitized substrate of claim 1 further including second and third conductive thru-holes, said second and third conductive thru-holes electrically coupling said first and second conductive ground lines to said substantially solid conductive ground plane, respectively.

7. The circuitized substrate of claim 1 further including additional dielectric and conductive layers as part thereof.

8. The circuitized substrate of claim 7 further including first and second pluralities of external conductive pads located on opposite sides of said circuitized substrate for electrically coupling said circuitized substrate to external electrical components.

9. The invention of claim 8 wherein said circuitized substrate is a chip carrier.

10. The invention of claim 8 wherein said circuitized substrate is a printed circuit board.

11. The circuitized substrate of claim 1 further including a third conductive signal line positioned on said second opposing side of said first dielectric layer adjacent said first conductive signal line, said first and second conductive ground lines and said substantially solid conductive ground plane also providing shielding for said third conductive signal line during the passage of electrical current through said third conductive signal line.

12. The circuitized substrate of claim 11 further including a conductive ground line positioned on said second opposing side of said first dielectric layer substantially between said first and third conductive signal lines, said conductive ground line also providing shielding for said first and third conductive signal lines during the passage of electrical current through said first and third conductive signal lines.

13. The circuitized substrate of claim 1 further including third and fourth dielectric layers positioned on said first and second dielectric layers, respectively, and second and third substantially solid conductive ground planes positioned on said third and fourth dielectric layers, respectively, said second and third substantially solid conductive ground planes also providing shielding for said at least one conductive signal line during the passage of electrical current through said signal line.

14. An electrical assembly comprising:

an electrical component; and

a printed circuit board including a circuitized substrate having first and second dielectric layers, each of said first and second dielectric layers having first and second opposing sides, a substantially solid conductive ground plane located between said first opposing side of said first dielectric layer and said first opposing side of said second dielectric layer, a first conductive signal line located on said second opposing side of said first dielectric layer and a second conductive line located on said second opposing side of said second dielectric layer; first and second conductive ground lines located on said second opposing side of said first dielectric layer on opposite sides of said first conductive signal line and electrically coupled to said substantially solid conductive ground plane located on said first opposing side of said dielectric layer, and a first conductive thru-hole extending through said substantially solid conductive ground plane and electrically coupling said first conductive signal line to said second conductive signal line, said first and second conductive ground lines and said substantially conductive ground plane providing shielding for said at least one conductive signal line during the passage of electrical current through said signal line, said electrical component being electrically coupled to said printed circuit board.

15. The electrical assembly of claim 14 wherein said electrical component is a chip carrier.

16. The electrical assembly of claim 14 wherein said electrical component is a semiconductor chip.

17. The electrical assembly of claim 14 wherein said circuitized substrate further includes second and third conductive thru-holes, said second and third conductive thru-holes electrically coupling said first and second conductive ground lines to said substantially solid conductive ground plane.

Assignments (14)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2008
From: WACHOVIA CAPITAL FINANCE CORPORATION
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 021861/0869 →