First and second microstrip networks stacked in an inverted arrangement to each other using an integrated support and shielding structure
View Patent ↗An assembly includes at least one first microstrip network having at least one first transmission line disposed on a first surface of a first dielectric layer including a first ground plane disposed on a second surface of the dielectric layer. At least one second microstrip network includes at least one second transmission line disposed on a first surface of a second dielectric layer, the second dielectric layer including a second ground plane disposed on a second surface of the second dielectric layer. The at least one second microstrip network is inverted relative to the at least one first microstrip network. At least one integrated support and shielding (ISS) structure is disposed between the second and the first microstrip network. The ISS structure includes a first cavity accommodating the first microstrip network and a second cavity accommodating the second microstrip network. The cavities are configured in accordance with RF performance criterions.
1. An assembly comprising:
at least one first microstrip network including at least one first transmission line disposed on a first surface of a first dielectric layer, the first dielectric layer including a first ground plane disposed on a second surface of the first dielectric layer;
at least one second microstrip network including at least one second transmission line disposed on a first surface of a second dielectric layer, the second dielectric layer including a second ground plane disposed on a second surface of the second dielectric layer, the at least one second microstrip network being inverted relative to the at least one first microstrip network;
at least one integrated support and shielding (ISS) structure disposed between the at least one second microstrip network and the at least one first microstrip network, the ISS structure including a first cavity accommodating the at least one first microstrip network and a second cavity accommodating at least one second microstrip network; and
wherein the first dielectric layer and the second dielectric layer are made from different dielectric materials.
2. The assembly of claim 1 , wherein at least one of said first dielectric layer and said second dielectric layer further comprises at least one alignment portion on the first surface thereof, wherein said alignment portion is configured receive an alignment pin from said at least one ISS structure.
3. The assembly of claim 1 , wherein at least one of the first surface of said first dielectric layer and the first surface of said second dielectric layer further comprises a bonding frame, wherein said bonding frame is structured to bond said at least one ISS structure to at least one of said first surface of said first dielectric layer and said second dielectric layer.
4. The assembly of claim 1 , wherein said at least one ISS structure is coupled to each of said at least one second microstrip network and said at least one first microstrip network by an attachment means.
5. The assembly of claim 1 , further comprising at least one interconnection device disposed between the at least one second microstrip network and the at least one first microstrip network.
6. The assembly of claim 5 , wherein at least one of said first dielectric layer and said second dielectric layer further comprises at least one alignment portion on the first surface thereof, wherein said alignment portion is configured receive an alignment pin from said at least one interconnection device.
7. The assembly of claim 5 , wherein said at least one interconnection device is configured to propagate RF signals between said at least one first microstrip network and said at least one second microstrip network, and is implemented using an interconnector.
8. The assembly of claim 1 , wherein each of said dielectric layer is formed from a dielectric material selected from the group consisting of FR-4, Alumina, high frequency laminates, titanium dioxide, magnesium-titanium alloys, and barium-titanium alloys.
9. The assembly of claim 1 , further comprising:
at least one third microstrip network disposed on top of said at least one second microstrip network and including at least one third transmission line disposed on a first surface of a third dielectric layer, the third dielectric layer including a third ground plane disposed on a second surface of the third dielectric layer.
10. The assembly of claim 9 , further comprising:
at least one fourth microstrip network including at least one fourth transmission line disposed on a first surface of a fourth dielectric layer, the fourth dielectric layer including a fourth ground plane disposed on a second surface of the second dielectric layer, the at least one fourth microstrip network being inverted relative to the at least one third microstrip network.
11. The assembly of claim 10 , further comprising
a second ISS structure disposed between the at least one fourth microstrip network and the at least one third microstrip network, the second ISS structure including a third cavity accommodating the at least one third microstrip network and a fourth cavity accommodating at least one fourth microstrip network.
12. The assembly of claim 1 , further comprising:
at least one third microstrip network laterally positioned to said at least one first microstrip network and including at least one third transmission line disposed on a first surface of a third dielectric layer, the third dielectric layer including a third ground plane disposed on a second surface of the third dielectric layer.
13. The assembly of claim 12 , further comprising:
at least one fourth microstrip network including at least one fourth transmission line disposed on a first surface of a fourth dielectric layer, the fourth dielectric layer including a fourth ground plane disposed on a second surface of the second dielectric layer, the at least one fourth microstrip network being inverted relative to the at least one third microstrip network.
14. The assembly of claim 13 , further comprising
a second ISS structure disposed between the at least one fourth microstrip network and the at least one third microstrip network, the second ISS structure including a third cavity accommodating the at least one third microstrip network and a fourth cavity accommodating at least one fourth microstrip network.