IP Library Granted Patent US 9,532,465
Granted Patent B2
US 9,532,465 · App. 13/852,947 · Granted Dec 27, 2016

Method of fabricating a printed circuit board interconnect assembly

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Quick Facts
Patent No.
US 9,532,465
App. No.
13/852,947
Granted
Dec 27, 2016
Kind
B2
Abstract

The invention provides a method of fabricating an interconnect comprising aligning and stacking a plurality of printed circuit boards with at least one adhesive component, laminating the printed circuit boards and the adhesive component, preparing bonded pair holes, depositing a copper seed layer, forming a copper plate image, electroplating a copper layer, removing a plate resist and depositing an insulator layer.

Claims (12)

1. A method of fabricating a printed circuit board interconnect assembly, comprising:

aligning and stacking a plurality of printed circuit boards with at least one adhesive component, each of the plurality of circuit boards including at least one tooling alignment hole,

the at least one adhesive component being pre-cut and comprising a first side and a second side and at least one tooled alignment hole;

laminating the printed circuit boards and the adhesive component so that the first side is interfaced with one of the plurality of printed circuit boards and the second side is interfaced to another of the plurality of printed circuit boards, and

wherein the at least one tooling alignment hole corresponds to the position of the at least one tooled alignment hole;

after laminating, preparing bonded pair holes;

after preparing, depositing a copper seed layer;

after depositing, creating at least one plate resist layer;

after creating, forming a copper plate image;

after forming, electroplating a copper layer;

after electroplating, removing the at least one plate resist layer; and

depositing an insulator layer after plate resist removal, resulting in the printed circuit board interconnect assembly.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (035858/0890) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TTM TECHNOLOGIES, INC. (FORMERLY KNOWN AS VIASYSTEMS GROUP, INC. AND VIASYSTEMS, INC.); TTM TECHNOLOGIES NORTH AMERICA, LLC (FORMERLY KNOWN AS VIASYSTEMS TECHNOLOGIES CORP., L.L.C.)
Reel/Frame 075681/0922 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE NAME OF THE ASSIGNEE PREVIOUSLY RECORDED AT REEL: 040637 FRAME: 0715. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 22, 2023
From: VESCE, JOHN; HEERY, JOSEPH WILLIAM, JR.
To: TTM TECHNOLOGIES, INC.
Reel/Frame 063722/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2016
From: VESCE, JOHN; HEERY, JOSEPH WILLIAM, JR.
To: TTM TECHNOLOGIES INC.
Reel/Frame 040637/0715 →