Granted Patent B2

US 7,145,221 · App. 10/920,235 · Granted Dec 5, 2006

Abstract

Claims (47)

1. A circuitized substrate comprising:

a first layer comprised of a dielectric material including a low moisture absorptive polymer resin material and a nodular fluoropolymer web encased within said low moisture absorptive polymer resin material, said first layer not including continuous or semi-continuous fibers as part thereof; and

at least one circuitized layer positioned on said first layer.

2. The circuitized substrate of claim 1 wherein said first layer includes a plurality of thru-holes therein, the aspect ratio of the thickness of said circuitized substrate to the diameter of each of said thru-holes being within the range of from about 2:1 to about 20:1.

3. The circuitized substrate of claim 1 wherein said low moisture absorptive polymer resin comprises a high Tg thermosetting polymer.

4. The circuitized substrate of claim 1 wherein said dielectric material has less than 0.15% moisture absorption when immersed in water for a period of about 24 hours at a temperature of about 22° C.

5. The circuitized substrate of claim 1 wherein said at least one circuitized layer is comprised of copper.

6. The circuitized substrate of claim 1 further including a second circuitized layer positioned on said first layer on a side opposite said at least one circuitized layer.

7. The circuitized substrate of claim 6 further including a plurality of conductive thru-holes in said first layer, selected ones of said conductive thru holes electrically coupling selected parts of said at least one circuitized layer to selected parts of said second circuitized layer.

8. The invention of claim 7 wherein said circuitized substrate comprises a chip carrier.

9. The circuitized substrate of claim 6 further including second and third dielectric layers positioned on said at least one circuitized layer and said second circuitized layer, respectively, and third and fourth circuitized layers formed on said second and third dielectric layer, respectively.

10. The circuitized substrate of claim 1 wherein said nodular fluoropolymer web comprises from about 10 to about 80 percent by volume of said first layer of dielectric material layer.

11. An electrical assembly comprising:

a circuitized substrate including a first layer comprised of a dielectric material including a low moisture absorptive polymer resin material and a nodular fluoropolymer web encased within said low moisture absorptive polymer resin material, said first layer not including continuous or semi-continuous fibers as part thereof;

at least one circuitized layer positioned on said first layer; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

12. The electrical assembly of claim 11 wherein said first layer of said circuitized substrate includes a plurality of thru-holes therein, the aspect ratio of thickness of said circuitized substrate to the diameter of each of said thru-holes being within the range of from about 2:1 to about 20:1.

13. The electrical assembly of claim 11 wherein said low moisture absorptive polymer resin comprises a high Tg thermosetting polymer.

14. The electrical assembly of claim 13 wherein said dielectric material has less than 0.15% moisture absorption when immersed in water for a period of about 24 hours at a temperature of about 22° C.

15. The electrical assembly of claim 14 wherein said at least one circuitized layer is comprised of copper.

16. The electrical assembly of claim 11 further including a second circuitized layer positioned on said first layer on a side opposite said at least one circuitized layer.

17. The electrical assembly of claim 16 further including a plurality of conductive thru-holes in said first layer, selected ones of said conductive thru-holes electrically coupling selected parts of said at least one circuitized layer to selected parts of said second circuitized layer.

18. The electrical assembly of claim 16 further including second and third dielectric layers positioned on said at least one circuitized layer and said second circuitized layer, respectively, and third and fourth circuitized layers formed on said second and third dielectric layer, respectively.

19. The electrical assembly of claim 11 wherein said circuitized substrate comprises a chip carrier and said at least one electrical component comprises a semiconductor chip.

20. The electrical assembly of claim 11 wherein said nodular fluoropolymer web comprises from about 10 to about 80 percent by volume of said first layer of dielectric material.

21. A method of making a circuitized substrate, said method comprising:

providing a first layer comprised of a dielectric material including a low moisture absorptive polymer resin and a nodular fluoropolymer web encased within said low moisture absorptive polymer resin, said first layer not including continuous or semi-continuous fibers as part thereof; and

positioning at least one circuitized layer on said first layer of said dielectric material.

22. The method of claim 21 further providing in said first layer a plurality of thru-holes, the aspect ratio of the thickness of said circuitized substrate to the diameter of each of said thru-holes being within the range of from about 2:1 to about 20:1.

23. The method of claim 22 wherein said plurality of thru-holes are provided within said first layer using a laser.

24. The method of claim 21 further including positioning a second circuitized layer on said first layer on a side opposite said at least one circuitized layer.

25. The method of claim 24 further including providing a plurality of conductive thru-holes in said first layer such that selected ones of said conductive thru holes electrically couple selected parts of said at least one circuitized layer to selected parts of said second circuitized layer.

26. The method of claim 21 further including electrically coupling at least one electrical component to said at least one circuitized layer on said first layer of said dielectric material.

27. A multilayered circuitized structure comprising:

a first circuitized substrate portion including a first layer having a first pattern of conductive thru-holes therein and comprised of a dielectric material including a low moisture absorptive polymer resin material and a nodular fluoropolymer web encased within said low moisture absorptive polymer resin material, said first layer not including continuous or semi-continuous fibers as part thereof; and

second and third circuitized substrate portions positioned on opposite sides of said first circuitized substrate portion, each having a second pattern of interconnecting thru-holes therein, said first circuitized substrate portion providing electrical interconnection between said second and third circuitized substrate portions, including interconnecting selected ones of said thru-holes in said second circuitized substrate portion with corresponding thru-holes within said third circuitized substrate portion.

28. The invention of claim 27 wherein said multilayered circuitized structure comprises a printed circuit board.

29. The invention of claim 27 wherein said multilayered circuitized structure comprises a chip carrier.

30. The multilayered circuitized structure of claim 29 further including at least one semiconductor chip positioned on or within said chip carrier and forming part thereof.

31. An information handling system comprising:

a housing;

a circuitized substrate positioned within said housing and including a first layer comprised of a dielectric material including a low moisture absorptive polymer resin material and a nodular fluoropolymer web encased within said low moisture absorptive polymer resin material, said first layer not including continuous fibers as part thereof;

at least one circuitized layer positioned on said first layer; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

32. The invention of claim 31 wherein said information handling system comprises a personal computer.

33. The invention of claim 31 wherein said information handling system comprises a mainframe computer.

34. The invention of claim 31 wherein said information handling system comprises a computer server.

Assignments (17)