IP Library Granted Patent US 7,176,383
Granted Patent B2
US 7,176,383 · App. 10/740,398 · Granted Feb 13, 2007

Printed circuit board with low cross-talk noise

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Quick Facts
Patent No.
US 7,176,383
App. No.
10/740,398
Granted
Feb 13, 2007
Kind
B2
Abstract

A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

Claims (15)

1. A printed circuit board comprising:

a substantially solid power plane having first and second opposing sides;

first and second dielectric layers located on said first and second opposing sides of said substantially solid power plane, respectively;

a first signal layer located on said first dielectric layer and including a plurality of substantially parallel signal lines running in at least two directions across said first signal layer from a first side of said printed circuit board to a second side of said printed circuit board, said first signal layer being substantially parallel to said substantially solid power plane; and

a second signal layer located on said second dielectric layer and including a plurality of substantially parallel signal lines running in the same said at least two directions as said signal lines of said first signal layer across said second signal layer from said first side of said printed circuit board to said second side of said printed circuit board and of a substantially similar pattern as said signal lines of said first signal layer, said second signal layer also being substantially parallel to

said substantially solid power plane, at least a predetermined large portion of the number of signal lines in said first signal layer being aligned with and substantially parallel to a corresponding large portion of said signal lines in said second signal layer, said power plane located substantially between said predetermined portions of said aligned and substantially parallel signal lines to substantially reduce crosstalk between said first and second signal layers.

2. The printed circuit board of claim 1 wherein said power plane includes a plurality of clearance openings therein.

3. The printed circuit board of claim 2 further including a plurality of conductive through holes electrically connecting selected ones of said predetermined portion of signal lines in said first signal layer to corresponding selected ones of said predetermined portion of signal lines in said second signal layer, each of said conductive through holes passing through a selected one of said clearance openings in said power plane and being electrically isolated from said power plane such that said signal lines on both of said first and second signal layers are not electrically coupled to said power plane.

4. The printed circuit board of claim 3 wherein the number of said conductive through holes is within the range of from about 1 to about 10,000.

5. The printed circuit board according to claim 1 wherein said power plane and said signal lines in said first and second signal layers are each comprised of copper.

6. The printed circuit board of claim 1 wherein said predetermined large portions of said signal lines in each of said first and second signal layers ranges from about 25 to about 95 percent of the total number of signal lines in each of said signal planes.

7. The printed circuit board of claim 1 further including third and fourth dielectric layers on said first and second signal layers, respectively, and third and fourth conductive layers on said third and fourth dielectric layers, respectively.

8. The printed circuit board of claim 1 wherein adjacent signal lines in each of said first and second signal layers are positioned as closely as only about 0.002 inch apart within said signal layers, each of said signal lines within said first signal layer being positioned only about 0.005 inch from the corresponding signal line within said second signal layer.

9. The printed circuit board of claim 8 wherein each of said signal lines has a thickness of from about 0.0005 inch to about 0.002 inch.

10. The printed circuit board of claim 1 wherein said at least two directions which said signal lines of both said first and second signal layers run across said signal layers include a first direction and a second direction substantially perpendicular to said first direction.

Assignments (17)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2008
From: WACHOVIA CAPITAL FINANCE CORPORATION
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 021861/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2007
From: WACHOVIA BANK, NATIONAL ASSOCIATION, AS AGENT
To: WACHOVIA CAPITAL FINANCE CORPORATION ( NEW ENGLAND), AS AGENT
Reel/Frame 019304/0676 →
SECURITY AGREEMENT Recorded May 10, 2005
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: WACHOVIA BANK, NATIONAL ASSOCIATION, AS AGENT
Reel/Frame 016561/0605 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2003
From: LAUFFER, JOHN M.; MARKOVICH, VOYA; MCNAMARA, JAMES J., JR.; THOMAS, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 014831/0295 →