IP Library Granted Patent US 7,791,897
Granted Patent B2
US 7,791,897 · App. 12/283,146 · Granted Sep 7, 2010

Multi-layer embedded capacitance and resistance substrate core

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Quick Facts
Patent No.
US 7,791,897
App. No.
12/283,146
Granted
Sep 7, 2010
Kind
B2
Abstract

A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

Claims (35)

1. A multi-layer embedded capacitance and resistance substrate core, comprising:

a) at least one layer of resistance material on a laser drillable dielectric, said one layer of resistance material having a patterned layer of electrically conductive material embedded therein;

b) a first patterned electrically conductive layer disposed on said first patterned resistance layer;

c) a capacitance layer disposed on said first patterned electrically conductive layer, said capacitance layer having non-uniform thickness;

d) a second resistance layer disposed on said capacitance layer; and a second electrically conductive layer disposed on said second resistance layer; and

e) a plurality of thru-holes formed by laser.

2. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , wherein said laser drillable dielectric material has a layer of resistance and capacitance material on both sides thereof.

3. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , wherein said at least one layer of capacitance material comprises a plurality of capacitance layers having variable capacitance density.

4. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , wherein said laser dielectric material has controlled CTE ranging from approximately 7-15 ppm.

5. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , wherein said conductive layer bonded to said capacitance layer comprises a layer of resistance material comprising a layer of electrically conductive material therein.

6. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , further comprising:

e) at least one other layer of capacitance material partially covering said substrate core, whereby a capacitance at a first predetermined position relative to said substrate is different from the capacitance at a second predetermined position relative to said substrate.

7. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , further comprising:

e) at least one other layer of resistance material partially covering said substrate core, whereby a resistance at a first predetermined position relative to said substrate is different from the resistance at a second predetermined position relative to said substrate.

8. The multi-layer embedded capacitance and resistance substrate core in accordance with claim 6 , further comprising:

f) at least one other layer of resistance material partially covering said substrate core, whereby a resistance at a first predetermined position relative to said substrate is different from the resistance at a second predetermined position relative to said substrate and whereby a capacitance at a third predetermined position relative to said substrate is different from the capacitance at a fourth predetermined position relative to said substrate.

9. An information handling system comprising a multi-layer embedded capacitance and resistance substrate core, said core comprising:

a) at least one layer of resistance material;

b) a first patterned electrically conductive layer disposed on said first patterned resistance layer;

c) a capacitance layer disposed on said first patterned electrically conductive layer, said capacitance layer having non-uniform thickness;

d) a second resistance layer disposed on said capacitance layer; and

e) a second electrically conductive layer disposed on said second resistance layer;

f) a plurality of thru-holes formed by laser.

10. The information handling system of claim 9 wherein said at least one layer of resistance material comprises dielectric material.

11. The information handling system of claim 9 wherein said at least one layer of capacitance material comprises a plurality of capacitance layers having variable capacitance density.

12. The information handling system of claim 10 wherein said at least one layer of capacitance material comprises a plurality of capacitance layers each having a different capacitance density.

13. The information handling system of claim 9 wherein the number of said layers of resistance material is greater than the number of said layer(s) of capacitance material by two.

14. A multi-layer embedded capacitance and resistance substrate core, comprising:

b) a first laser-drillable dielectric layer;

c) a first patterned resistance layer disposed on said first dielectric layer;

d) a first patterned electrically conductive layer disposed on said first patterned resistance layer;

e) a capacitance layer disposed on said first patterned electrically conductive layer;

f) a second resistance layer disposed on said capacitance layer; and

g) a second electrically conductive layer disposed on said second resistance layer;

whereby a crenellated capacitance layer is formed between said first laser-drillable dielectric layer and said second electrically conductive layer.

Assignments (12)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: DAS, RABINDRA N.; LAUFFER, JOHN M.; MEMIS, I. (NMN); ROSSER, STEVEN G.
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 021543/0698 →