IP Library Granted Patent US 8,198,739
Granted Patent B2
US 8,198,739 · App. 12/836,612 · Granted Jun 12, 2012

Semi-conductor chip with compressible contact structure and electronic package utilizing same

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Quick Facts
Patent No.
US 8,198,739
App. No.
12/836,612
Granted
Jun 12, 2012
Kind
B2
Abstract

A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

Claims (23)

1. A method of forming a compressible contact structure on a semi-conductor chip, said method comprising:

providing a semi-conductor chip having at least one substantially planar surface including a plurality of individual contacts thereon;

bonding a compressible polymer layer to said at least one substantially planar surface including said plurality of individual contacts thereon to substantially cover said plurality of individual contacts, said polymer layer having an outer surface;

forming a plurality of openings within said compressible polymer layer, each of said openings extending through said compressible polymer layer from said outer surface to expose a corresponding one of said individual contacts;

depositing electrically conductive material within said plurality of openings to form electrical connections with said individual contacts and a plurality of electrically conductive line elements on said outer surface of said compressible polymer layer, each of said conductive line elements extending from a respective one of said openings a predetermined distance from said opening and including an end portion; and

forming a plurality of contact members each on a respective one of said end portions of said conductive line elements, said compressible polymer layer allowing said plurality of contact members to deflect toward said substantially planar surface of said semi-conductor chip when said plurality of contact members are acted upon by an external force.

2. The method of claim 1 wherein said bonding of said compressible polymer layer to said at least one substantially planar surface of said semi-conductor chip comprises depositing an adhesive layer on said substantially planar surface and thereafter positioning said compressible polymer layer atop said adhesive layer.

3. The method of claim 1 wherein said forming of said plurality of openings within said compressible layer is accomplished using at least one of the group: laser ablation and photolithographic processing.

4. The method of claim 1 wherein said depositing of said electrically conductive material within said plurality of openings to form said electrical connections with said individual contacts and said plurality of electrically conductive line elements on said outer surface of said compressible polymer layer is accomplished using at least one of the group: sputter deposition, electroless plating, and electrolytic plating.

5. method of claim 1 wherein said forming of said plurality of contact members each on a respective one of said end portions of said conductive line elements is accomplished using at least one of the group: sputter deposition, electroless plating, and electrolytic plating.

6. The method of claim 1 further including aligning each of said contact members on said end portions of said conductive line elements with a respective contacting member on a circuitized substrate and thereafter pressing said semi-conductor chip and said circuitized substrate together to form a plurality of separable electrical connections between said contact members and said contacting members.

7. The method of claim 1 further including forming a solder element on each of said contact members on said end portions of said conductive line elements.

8. The method of claim 7 further including aligning said solder elements on said each of said contact members on said end portions of said conductive line elements with a respective contacting member on a circuitized substrate and thereafter heating said solder elements to form an electrical coupling between each of said contact members and said respective contacting members.

9. A semiconductor chip including at least one substantially planar surface having a plurality of individual contacts thereon and a compressible contact structure, said compressible contact structure comprising a compressible polymer layer bonded to said at least one substantially planar surface, said polymer layer having an outer surface, a plurality of openings within said compressible polymer layer, each of said openings extending through said compressible polymer layer from said outer surface to expose a corresponding one of said individual contacts, electrically conductive material within said plurality of openings in electrical connection with said individual contacts and a plurality of electrically conductive line elements on said outer surface of said compressible polymer layer, each of said conductive line elements extending from a respective one of said openings a predetermined distance from said opening and including an end portion, and a plurality of contact members each on a respective one of said end portions of said conductive line elements, said compressible polymer layer allowing said plurality of contact members to deflect toward said substantially planar surface of said semi-conductor chip when said plurality of contact members is acted upon by an external force.

10. The semi-conductor chip of claim 9 wherein said compressible polymer layer comprises polyester film material.

11. The semi-conductor chip of claim 9 wherein said electrically conductive material within said plurality of openings in electrical connection with said individual contacts of said semi-conductor chip comprises at least one of the group:

copper and copper alloy.

12. The semi-conductor chip of claim 9 wherein said plurality of electrically conductive line elements on said outer surface of said compressible polymer layer comprise at least one of the group: copper and copper alloy.

13. The semi-conductor chip of claim 9 wherein said plurality of contact members each on a respective one of said end portions of said conductive line elements comprise at least one of the group: copper and copper alloy.

14. The semi-conductor chip of claim 9 further including a circuitized substrate having a plurality of contacting members on said circuitized substrate, each of said contact members adapted for engaging respective ones of said contacting members of said circuitized substrate to form separable electrical connections between said contact members and said contacting members when said semi-conductor chip and said circuitized substrate are pressed together, said semi-conductor chip and said circuitized substrate comprising an electronic package.

15. The semi-conductor chip of claim 9 further including a solder element on each of said contact members on said end portions of said conductive line elements.

16. The semi-conductor chip of claim 15 further including a circuitized substrate having a plurality of contacting members on said circuitized substrate, each of said solder elements forming an electrical coupling between each of said contact members and said respective contacting members.

17. The invention of claim 16 wherein said semi-conductor chip, said solder elements and said circuitized substrate comprise an electronic package.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2012
From: LIN, HOW; EGITTO, FRANK; MARKOVICH, VOYA
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028142/0283 →