IP Library Granted Patent US 7,910,156
Granted Patent B2
US 7,910,156 · App. 11/730,212 · Granted Mar 22, 2011

Method of making circuitized substrate with selected conductors having solder thereon

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Quick Facts
Patent No.
US 7,910,156
App. No.
11/730,212
Granted
Mar 22, 2011
Kind
B2
Abstract

A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.

Claims (16)

1. A method of making a circuitized substrate, said method comprising:

providing a substrate including at least one dielectric layer having an external surface and a first plurality of conductors and a second plurality of conductors on said external surface;

applying a photo-resist covering over said first plurality of conductors but not over said second plurality of conductors on said external surface of said substrate;

applying a layer of sacrificial solder-resist material over said photo-resist covering;

exposing said first plurality of conductors having said photo-resist covering and said layer of solder-resist material thereon and said second plurality of conductors not having said photo-resist covering thereon to a quantity of molten solder so as to deposit said solder onto only said second plurality of conductors; and

thereafter removing said layer of solder-resist material on said photo-resist covering and said photo-resist covering over said first plurality of conductors.

2. The method of claim 1 wherein said applying of said photo-resist covering over said first plurality of conductors but not over said second plurality of conductors on said external surface of said substrate is accomplished using a lamination process.

3. The method of claim 2 wherein said lamination process is accomplished at a temperature within the range of from about 75 degrees Celsius to about 95 degrees Celsius for a time period of from about sixty to about eighty seconds.

4. The method of claim 1 wherein said applying said layer of sacrificial solder-resist material over said photo-resist covering is accomplished by selective screen printing and curing at a temperature within the range of from about 120 degrees Celsius to about 150 degrees Celsius for a time period of about ten to twenty minutes.

5. The method of claim 1 wherein said exposing said first plurality of conductors having said photo-resist covering and said layer of solder-resist material thereon and said second plurality of conductors not having said photo-resist covering thereon to said quantity of molten solder is accomplished by immersing said substrate within a bath of said solder.

6. The method of claim 1 wherein said removing said layer of solder-resist material on said photo-resist covering photo-resist and said removing of said photo-resist covering is accomplished using a chemical process.

7. The method of claim 6 wherein said removing said layer of solder-resist material on said photo-resist covering photo-resist is accomplished using a manual peeling operation.

8. The method of claim 6 wherein said removing of said photo-resist covering is accomplished using a chemical stripping operation.

9. The method of claim 1 , wherein said substrate comprises thru-holes therein, said thru-holes being filled with conductive paste.

10. The method of claim 9 wherein selected ones of said first plurality of conductors are formed on said substrate over respective ones of said thru-holes.

11. The method of claim 1 further including using hot air leveling to substantially level said solder deposited onto only said second plurality of conductors before said removing said layer of solder-resist material on said photo-resist covering and said photo-resist covering over said first plurality of conductors.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2007
From: CARD, NORMAN A.; HARENDZA, ROBERT J.; KONRAD, JOHN J.; MOSHER, TONYA L.; PITELY, SUSAN; RIOS, JOSE A.
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 019138/0749 →