Coreless layer buildup structure
View Patent ↗A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
1. A coreless substrate for use in a PC board comprising:
a) an etched first metal layer having a first and a second surface;
b) at least two coreless, partially-filled thermoset resin-coated CU-based buildup layers disposed respectively on said first and said second surfaces;
c) a second and a third metal layer disposed on said at least two coreless buildup layers, respectively; and
d) an electrical connection between said first and said second metal layers, and said first and said third metal layers, and said second and said third metal layers;
whereby a high density, thin, coreless substrate is produced.
2. The coreless substrate as per claim 1 , wherein said at least two coreless buildup layers comprise a partially-cured fiberglass cloth-impregnated, filled thermoset resin.
3. The coreless substrate as per claim 1 , wherein said at least two coreless buildup layers comprise a thermoplastic resin.
4. The coreless substrate as per claim 2 , wherein said at least two coreless buildup layers comprise alternate layers of partially-cured and fully-cured resin.
5. The coreless substrate as per claim 1 , further comprising:
e) a first joining layer of dielectric disposed between said first and said second metal layers.
6. The coreless substrate as per claim 5 , wherein said first and said second metal layers each comprises two to six metal layers.
7. The coreless substrate as per claim 5 , wherein said first joining layer of dielectric comprises at least one from the group: partially-cured thermoset resin and thermoplastic.
8. The coreless substrate as per claim 5 , wherein said first joining layer of dielectric comprises at least one from the group: high dielectric constant and low loss capacitance material.
9. The coreless substrate as per claim 5 , wherein said first and said second metal layers comprise resistor foil laminated and circuitized on at least one from the group: at least partially-cured thermoset and thermoplastic resin dielectric layer.
10. The coreless substrate as per claim 6 , wherein said first and said second metal layers comprise a multilayer resistor foil.
11. The coreless substrate as per claim 10 , wherein said multilayer resistor foil comprises a resistance range of 15 ohms to 30,000 ohms.
12. The coreless substrate as per claim 9 , wherein said multilayer resistor foil comprises at least one from the group: high dielectric constant and low loss capacitance layer.
13. The coreless substrate as per claim 5 , further comprising;
f) a third metal layer.
14. The coreless substrate as per claim 13 , further comprising:
g) a second joining layer of dielectric disposed between said second and said third metal layers.
15. The coreless substrate as per claim 14 , wherein said second joining layer of dielectric comprises capacitance material.
16. The coreless substrate as per claim 13 , wherein said first and said second and said third metal layers comprise at least one from the group: signal, power, and ground.
17. The coreless substrate as per claim 13 , further comprising conductive paste comprising at least one set of metal micro particles chosen from the group: copper, silver, gold, zinc, cadmium, palladium, iridium, ruthenium, osmium, rhodium, platinum, iron, cobalt, nickel, indium, tin, antimony, lead, bismuth and alloys thereof.
18. The coreless substrate as per claim 17 , wherein the decomposition temperature of said conductive paste is approximately 340° C.