CONDUCTIVE METAL MICRO-PILLARS FOR ENHANCED ELECTRICAL INTERCONNECTION

1 . A method of forming a circuitized substrate for use in electronic packages, the steps comprising:

a) providing a substrate layer having an upper surface and a lower surface;

b) disposing a copper layer on said upper surface of said substrate layer;

c) forming an interconnect pad on said copper layer;

d) disposing a conductive seed layer on said upper surface of said substrate layer;

e) disposing a photoresist layer on said conductive seed layer;

f) developing electrical features on said photoresist layer;

g) disposing a first conductive material within said features of said photoresist layer;

h) disposing a second conductive material on said first conductive material; and

i) removing said photoresist layer and said conductive seed layer.

2 . The method of forming a circuitized substrate as in claim 1 , wherein said disposing step (h) and said removing step (i) are performed in reverse order.

3 . The method of forming a circuitized substrate as in claim 1 , wherein said first conductive material comprises an approximately 1 - 100 micron thick layer of copper.

4 . The method of forming a circuitized substrate as in claim 1 , wherein said second conductive material further comprises:

i) a tin solder material;

ii) a tin-lead solder material;

iii) a tin-gold solder material; and

iv) a tin-silver solder material.

5 . A method of forming a circuitized substrate for use in electronic packages, the steps comprising:

a) providing a substrate layer having an upper surface and a lower surface;

b) disposing a copper layer on said upper surface of said substrate layer;

c) forming an interconnect pad on said copper layer;

d) disposing a conductive seed layer on said upper surface of said substrate layer; and

e) disposing an object on said conductive seed layer, said object selected from at least one of the group comprising: carbon, metal alloy, nanotube, nanowire, nanofiber, micro-fiber, micro-tube, and micro-wire.

6 . The method of forming a circuitized substrate as in claim 5 , wherein said conductive seed layer comprises gold.

7 . A circuitized substrate for use in electronic packages comprising:

a first circuitized substrate layer having a first surface containing a copper interconnect pad having a first plurality of micro-pillars disposed on a surface thereof;

a second circuitized substrate layer having a second surface containing a copper interconnect pad having a second plurality of micro-pillars disposed on a surface thereof; and

said micro-pillars of said first circuitized substrate layer and said second circuitized substrate layer being aligned and interfaced prior to lamination.

8 . The circuitized substrate of claim 7 , wherein said micro-pillars comprise conductive metal.

9 . The circuitized substrate of claim 7 , further comprising a conductive paste disposed on said first plurality of micro-pillars and on said second plurality of micro-pillars.

10 . A method of forming an electrically conducting adhesive (ECA) or paste mixture with high metal loading, the method comprising:

a) embedding a nanoparticle within a polymer constituent by adding a resin to a silver nanoparticle solution in a low temperature boiling solvent;

b) dissolving said polymer constituent containing said nanoparticles in said silver nanoparticle solution by evaporating said low temperature boiling solvent to form an embedded nanoparticle polymer;

c) combining said embedded nanoparticle polymer constituent with dry micro powder and an anhydride; and

d) mixing said embedded nanoparticle polymer, anhydride, and micro powder.

11 . The method of claim 10 , wherein said embedding step (a) further comprises adding micro particles with said nanoparticles in said solvent.

12 . The method of claim 10 , wherein said dissolving step (b) further comprises drying said solvent under a vacuum to evaporate said solvent.

13 . An information handling system (IHS) comprising:

a housing; and

a circuitized substrate positioned substantially within said housing and including a first circuitized substrate layer having a first surface containing a copper interconnect pad having a first plurality of micro-pillars disposed on a surface and a second circuitized substrate layer having a second surface containing a copper interconnect pad having a second plurality of micro-pillars disposed on a surface and electrically connecting said micro-pillars of said first circuitized substrate layer and said second circuitized substrate layer for Z-axis interconnects of circuitized substrates.

14 . The IHS of claim 13 , wherein said IHS comprises an object selected from at least one of the group comprising: personal computer, mainframe computer, and computer server.