Method of making wirebond electronic package with enhanced chip pad design
View Patent ↗A method of making a wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow.
1. A method of making a wirebond electronic package, said method comprising:
providing an organic laminate substrate having an external surface;
forming an electrically conductive circuit on said external surface of said organic laminate substrate including a plurality of wirebond pads;
forming a pattern of thermally conductive material on said external surface of said organic laminate relative to said wirebond pads of said electrical circuit, said pattern of thermally conductive material including a plurality of substantially concentric, spaced-apart lines;
positioning a semiconductor chip on said external surface of said organic laminate substrate and bonding said semiconductor chip to said external surface of said organic laminate substrate and said plurality of substantially concentric, spaced-apart lines of said pattern of thermally conductive material such that said semiconductor chip is thermally coupled to said plurality of concentric, spaced-apart lines of said pattern of thermally conductive material; and
electrically connecting said semiconductor chip to said plurality of said wirebond pads.
2. The method of claim 1 wherein said forming of said electrically conductive circuit on said external surface of said organic laminate substrate is accomplished using photolithographic processing.
3. The method of claim 1 wherein said forming of said pattern of thermally conductive material on said external surface of said organic laminate substrate relative to said wirebond pads is accomplished simultaneously with said forming of said electrically conductive circuit.
4. The method of claim 1 wherein said positioning of said semiconductor chip on said external surface of said organic laminate substrate such that said semiconductor chip is bonded to said substrate and is thermally coupled to said plurality of concentric, spaced-apart lines of said pattern of thermally conductive material includes utilizing a quantity of adhesive.
5. The method of claim 1 further including providing a plurality of thermally conductive members within said organic laminate substrate in thermal connection to said concentric lines of said pattern of said thermally conductive material.
6. The method of claim 5 further including forming a plurality of openings within said organic dielectric substrate and providing said plurality of said thermally conductive members within said plurality of openings.