CIRCUITIZED SUBSTRATE WITH INTERNAL THIN FILM CAPACITOR AND METHOD OF MAKING SAME
A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided.
1 . A circuitized substrate comprising:
a capacitive substrate including at least one electrically conductive layer, a low dielectric constant silica-based ceramic thin film layer of capacitor material disposed on said at least one electrically conductive layer, and at least one electrically conductive element positioned on a first surface of said low dielectric constant silica-based ceramic thin film layer adjacent said at least one electrically conductive layer; and
at least one low dielectric constant organic-based dielectric layer positioned on said capacitive substrate, said at least one electrically conductive layer, said low dielectric constant silica-based ceramic thin film layer, and said at least one electrically conductive element forming a first capacitor within said circuitized substrate during operation thereof, said low dielectric constant silica-based ceramic thin film layer blending with said at least one low dielectric constant organic-based dielectric layer and acting as a single dielectric layer without significant interference of signal performance.
2 . The circuitized substrate of claim 1 , further comprising a second low dielectric constant silica-based ceramic thin film layer and including a second electrically conductive element positioned thereon adjacent said at least one electrically conductive layer and low dielectric constant organic-based dielectric layer, said second electrically conductive element, said second low dielectric constant silica-based ceramic thin film layer and said at least one electrically conductive layer forming a second capacitor within said circuitized substrate during operation thereof, said second low dielectric constant silica-based ceramic thin film layer without said second electrically conductive layer blending with said second low dielectric constant organic-based dielectric layer and acting as a single dielectric without significant interference of signal performance.
3 . The circuitized substrate of claim 2 , further including a hole within said at least one conductive layer having at least one internal surface, said thin film layer being positioned on said at least one internal surface of said hole, and electrically conductive material positioned on said thin film layer of capacitor material positioned on said at least one internal surface of said hole, said electrically conductive material, said thin film layer positioned on said at least one internal surface of said hole and said at least one conductive layer forming a third capacitor within said circuitized substrate during operation of said circuitized substrate.
4 . The circuitized substrate of claim 3 , wherein the capacitance of each of said first, second and third capacitors is within the range of from about 7 nano-farads/square inch to about 2 micro-farads/square inch.
5 . The circuitized substrate of claim 1 , further including a hole within said at least one conductive layer having at least one internal surface, said thin film layer being positioned on said at least one internal surface of said hole, and electrically conductive material positioned on said thin film layer positioned on said at least one internal surface of said hole, said electrically conductive material, said thin film layer of capacitor material positioned on said at least one internal surface of said hole and said at least one conductive layer forming a second capacitor within said circuitized substrate during operation of said circuitized substrate.
6 . The circuitized substrate of claim 1 , wherein said thin film layer of capacitor material is selected from the group consisting of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, barium titanate, strontium tinanate, lead zirconate titanate, lead magnesium niobate, lead magnesium niobate-lead titanate, lead iron niobate, lead zinc niobate, and combinations thereof.
7 . The circuitized substrate of claim 1 , wherein the capacitance of said first capacitor is within the range of from about 7 nano-farads/square inch to about 2 micro-farads/square inch.
8 . The circuitized substrate of claim 1 , further including at least one electrical component positioned on said circuitized substrate and electrically coupled to said first capacitor within said circuitized substrate, said circuitized substrate and said at least one electrical component comprising an electronic package.
9 . A method of making a circuitized substrate comprising:
providing an electrically conductive layer including upper and lower opposing surfaces;
depositing a thin film layer of capacitor material on said upper and lower opposing surfaces of said electrically conductive layer;
bonding a pair of electrically conductive elements to said thin film layer, a first of said electrically conductive elements located on said capacitor material on said upper opposing surface of said electrically conductive layer and a second of said electrically conductive elements located on said capacitor material on said lower opposing surface of said electrically conductive layer to form a capacitive substrate including said electrically conductive layer, said thin film layer on said upper and lower opposing surfaces of said electrically conductive layer and said electrically conductive elements; and
bonding at least one dielectric layer onto said capacitive substrate to substantially cover at least one of the group: said first electrically conductive element and second electrically conductive element.
10 . The method of claim 9 , wherein said depositing of said thin film layer is accomplished by sputtering.
11 . The method of claim 9 , wherein said depositing of said thin film layer is accomplished by a process selected from the group: chemical vapor deposition, metal organic chemical vapor deposition, anodizing, self assembly, solution coating on self assembled monolayer, ink-jet printing, sol-gel coating, thermal evaporation, pulsed laser deposition, solution coating, spin coating, and combinations thereof.
12 . The method of claim 9 , wherein said bonding of said pair of electrically conductive elements to said thin film layer is accomplished by at least one of the group: sputtering, plating, and electrolytic plating.
13 . The method of claim 9 , further including forming a hole within said electrically conductive layer extending through said electrically conductive layer from said upper opposing surface to said lower opposing surface, said depositing of said thin film layer on said upper and lower opposing surfaces of said electrically conductive layer including depositing said capacitor material on the walls of said hole.
14 . The method of claim 9 , wherein said bonding said at least one dielectric layer onto said capacitive substrate to substantially cover said first and/or second electrically conductive elements is accomplished by lamination.
15 . A method of making a circuitized substrate comprising:
providing an electrically conductive layer including upper and lower opposing surfaces;
forming a hole having walls within said electrically conductive layer extending through said electrically conductive layer from said upper opposing surface to said lower opposing surface;
depositing a thin film layer of capacitor material on said upper and lower opposing surfaces of said electrically conductive layer and onto the walls of said hole;
bonding a pair of electrically conductive elements to said thin film layer, a first of said electrically conductive elements located on said capacitor material on said upper opposing surface of said electrically conductive layer and a second of said electrically conductive elements located on said capacitor material on said lower opposing surface of said electrically conductive layer to form a capacitive substrate including said electrically conductive layer, said thin film layer on said upper and lower opposing surfaces of said electrically conductive layer and said electrically conductive elements; and
bonding first and second dielectric layers each having a conductive layer thereon onto said capacitive substrate so as to force portions of said dielectric material of said first and second dielectric layers into said hole within said electrically conductive layer, other portions of said dielectric material of said first and second dielectric layers substantially covering said first and second electrically conductive elements.
16 . The method of claim 15 , wherein said depositing of said thin film layer is accomplished by a process selected from the group: consisting of chemical vapor deposition, metal organic chemical vapor deposition, ink-jet printing, sol-gel coating, thermal evaporation, pulsed laser deposition, sputtering, solution coating and spin coating.
17 . The method of claim 15 , wherein said bonding of said pair of electrically conductive elements to said thin film layer is accomplished by at least one of the group: sputtering, plating, and electrolytic plating.
18 . The method of claim 15 , wherein said forming of said hole having said walls within said electrically conductive layer is accomplished by a process selected from the group: drilling, punching, and etching.