Method of making circuitized substrate
View Patent ↗A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.
1. A method of making a circuitized substrate, said method comprising:
providing a first dielectric layer having a first surface;
forming a first pattern of conductors and a second pattern of conductors spaced from said first pattern and electrically coupled thereto on said first surface of said first dielectric layer;
forming a common conductive line and a plurality of second conductive lines on said first surface of said first dielectric layer, each of said second conductive lines electrically connecting one of said conductors of said second pattern of conductors to said common conductive line;
positioning a second dielectric layer over said first and second patterns of conductors and common conductive line;
providing openings in said second dielectric layer using a laser to expose at least portions of said second conductive lines which electrically couple said second pattern of conductors to said common conductive lines; and
thereafter severing said portions of said second conductive lines which electrically couple said second pattern of conductors to said common conductive line.
2. The method of claim 1 wherein said severing of said portions of said second conductive lines is accomplished by etching.
3. The method of claim 1 wherein said second dielectric layer is provided in solid form and laminated onto said first dielectric layer.
4. The method of claim 3 wherein said second dielectric layer comprises a soldermask.
5. The method of claim 1 wherein said first and second pattern of conductors and said common conductive line are formed using electrolytic plating.
6. The method of claim 1 further including positioning a semiconductor chip on said first dielectric layer and electrically coupling said semiconductor chip to said first pattern of conductors.
7. The method of claim 6 wherein said electrically coupling of said semiconductor chip to said first pattern of conductors is accomplished using a wirebonding operation.
8. The method of claim 6 wherein said semiconductor chip is electrically coupled to said first pattern of conductors using a plurality of solder balls.
9. A method of making a circuitized substrate, said method comprising:
providing a first dielectric layer having a first surface and a second opposing surface;
forming a first pattern of conductors and a second pattern of conductors spaced from said first pattern and electrically coupled thereto on said first surface of said first dielectric layer;
forming a common conductive line and a plurality of second conductive lines on said second opposing surface of said first dielectric layer, each of said second conductive lines electrically connecting one of said conductors of said second pattern of conductors to said common conductive line;
positioning a second dielectric layer over said first and second patterns of conductors and a third dielectric layer over said common conductive line and said second conductive lines;
providing openings in said third dielectric layer using a laser to expose at least portions of said second conductive lines which electrically couple said second pattern of conductors to said common conductive line; and
thereafter severing said portions of said second conductive lines which electrically couple said second pattern of conductors to said common conductive line.
10. The method of claim 9 wherein said severing of said portions of said second conductive lines is accomplished by etching.
11. The method of claim 10 wherein said second dielectric layer is provided in liquid form and flowed onto said first dielectric layer.
12. The method of claim 11 wherein said second and third dielectric layers each comprise a soldermask.
13. The method of claim 9 wherein said first and second pattern of conductors and said common conductive line are formed using electrolytic plating.
14. The method of claim 9 further including positioning a semiconductor chip on said first dielectric layer and electrically coupling said semiconductor chip to said first pattern of conductors.
15. The method of claim 14 wherein said electrically coupling of said semiconductor chip to said first pattern of conductors is accomplished using a wirebonding operation.
16. The method of claim 14 wherein said semiconductor chip is electrically coupled to said first pattern of conductors using a plurality of solder balls.
17. A method of making a circuitized substrate, said method comprising:
providing a first dielectric layer having a first surface and a second opposing surface;
forming a first pattern of conductors on said first surface and a second pattern of conductors on said second opposing surface and electrically coupled to said first pattern of conductors on said first dielectric layer;
forming a common conductive line and a plurality of second conductive lines on said second opposing surface of said first dielectric layer, each of said second conductive lines electrically connecting one of said conductors of said second pattern of conductors to said common conductive line;
positioning a second dielectric layer over said first pattern of conductors and a third dielectric layer over said second pattern of conductors, said common conductive line and said second conductive lines;
providing openings in said third dielectric layer using a laser to expose at least portions of said second conductive lines which electrically couple said second pattern of conductors to said common conductive lines; and
thereafter severing said portions of said second conductive lines which electrically couple said second pattern of conductors to said common conductive line.
18. The method of claim 17 wherein said severing of said portions of said second conductive lines is accomplished by etching.
19. The method of claim 17 wherein said second dielectric layer is provided in liquid form and flowed onto said first dielectric layer.
20. The method of claim 19 wherein said second and third dielectric layers each comprise a soldermask.
21. The method of claim 17 wherein said first and second pattern of conductors and said common conductive line are formed using electrolytic plating.
22. The method of claim 17 further including positioning a semiconductor chip on said first dielectric layer and electrically coupling said semiconductor chip to said first pattern of conductors.
23. The method of claim 22 wherein said electrically coupling of said semiconductor chip to said first pattern of conductors is accomplished using a wirebonding operation.
24. The method of claim 22 wherein said semiconductor chip is electrically coupled to said first pattern of conductors using a plurality of solder balls.