Method of making a semiconductor radiation detector
View Patent ↗A method of making a semiconductor radiation detector wherein the metal layers which serve as the cathode and anode electrodes are recessed from the designated prospective dice lines which define the total upper and lower surface areas for each detector such that the dicing blade will not directly engage the metal during dicing and therefore prevent metal from intruding upon (smearing) the vertical side walls of the detector substrate.
1. A method of making a semiconductor radiation detector comprising:
providing a semiconductor substrate having substantially planar upper and lower opposing surfaces having first and second surface areas respectively, said first and second surface areas being defined by prospective dice lines;
forming a first metal layer on said substantially planar upper surface such that said first metal layer will have a surface area less than said first surface area of said substantially planar upper surface as defined by spaces on said substantially planar upper surface between said first metal layer and said prospective dice lines which define said first surface area;
forming a second metal layer on said substantially planar lower opposing surface; and
dicing said semiconductor substrate through said prospective dice lines to produce a semiconductor radiation detector having substantially planar upper and lower opposing surfaces wherein said planar upper opposing surface is of a third surface area substantially similar to said surface layer of said first metal layer, said semiconductor radiation detector further including substantially perpendicular side walls.
2. The method of claim 1 , wherein said first metal layer is formed on said substantially planar upper surface using a process selected from the group consisting of evaporation, electro-less deposition and sputtering.
3. The method of claim 2 , wherein said spaces between said first metal layer and said prospective dice lines are formed using photolithographic processing.
4. The method of claim 1 , wherein said dicing is performed using a dicing blade.
5. The method of claim 4 , wherein said spaces have a predetermined width and said dicing blade has a thickness, the ration of said predetermined width of said spaces to said thickness of said dicing blade within the range of from about 100:1 to about 10:1.
6. A method of making a semiconductor radiation detector, the method comprising:
providing a semiconductor substrate having substantially planar upper and lower opposing surfaces having first and second surface areas respectively, said first and second surface areas being defined by prospective dice lines;
forming a first metal layer on said substantially planar upper surface such that said first metal layer will have a surface area less than said first surface area of said substantially planar upper surface as defined by spaces on said substantially planar upper surface between said first metal layer and said prospective dice lines which define said first surface area;
forming a second metal layer on said substantially planar lower opposing surface such that said second metal layer will have a surface area less than said second surface area of said substantially planar lower surface as defined by spaces on said substantially planar lower surface between said second metal layer and said prospective dice lines which define said second surface area; and
dicing said semiconductor substrate through said prospective dice lines to produce a semiconductor radiation detector having substantially planar upper and lower opposing surfaces wherein said planar upper opposing surface is of a third surface area substantially similar to said surface layer of said first metal layer, said semiconductor radiation detector further including substantially perpendicular side walls.
7. The method of claim 6 , wherein each of said first metal layer and said second metal layer is formed using a process selected from the group consisting of evaporation, electro-less deposition and sputtering.
8. The method of claim 6 , wherein said first and second metal layers are formed simultaneously.
9. The method of claim 6 , wherein at least one of the forming said first metal layer step and the forming said second metal layer step comprises using photolithographic processing.
10. The method of claim 6 , wherein said dicing is performed using a dicing blade.
11. The method of claim 10 , wherein said spaces have a predetermined width and said dicing blade has a thickness, the ratio of said predetermined width of said spaces to said thickness of said dicing blade is within the range of from about 100:1 to about 10:1.
12. The method of claim 1 , wherein the semiconductor substrate is a single semiconductor material.
13. The method of claim 12 , wherein the material comprises bulk-detecting crystals.
14. The method of claim 12 , wherein the material is chosen from the group consisting of CdTe, CdZnTn, lead iodide, silicon, gallium arsenide, and thallium bromide.
15. The method of claim 12 , wherein each of said first metal layer and said second metal layer is formed using a process selected from the group consisting of evaporation, electro-less deposition and sputtering.
16. The method of claim 12 , wherein said dicing is performed using a dicing blade.
17. The method of claim 16 , wherein said spaces have a predetermined width and said dicing blade has a thickness, the ratio of said predetermined width of said spaces to said thickness of said dicing blade is within the range of from about 100:1 to about 10:1.
18. The method of claim 12 , further including forming said second metal layer on said substantially planar lower surface such that said second metal layer will have a surface area less than said second surface area of said substantially planar lower surface as defined by spaces on said substantially planar lower surface between said second metal layer and said prospective dice lines.
19. The method of claim 1 , wherein the step of dicing said semiconductor substrate through said prospective grid lines comprises dicing completely through said semiconductor substrate from said substantially planar upper surface to said substantially planar lower opposing surface through said prospective dice lines.
20. The method of claim 19 , wherein said first metal layer is formed on said substantially planar upper surface using a process selected from the group consisting of evaporation, electro-less deposition and sputtering.
21. The method of claim 19 , wherein said dicing is performed using a dicing blade.
22. The method of claim 21 , wherein said spaces have a predetermined width and said dicing blade has a thickness, the ratio of said predetermined width of said spaces to said thickness of said dicing blade is within the range of from about 100:1 to about 10:1.
23. The method of claim 19 , further including forming said second metal layer on said substantially planar lower surface such that said second metal layer will have a surface area less than said second surface area of said substantially planar lower surface as defined by spaces on said substantially planar lower surface between said second metal layer and said prospective dice lines.