Insulated gate semiconductor device with small feedback capacitance and manufacturing method thereof

1. An insulated gate semiconductor device, comprising:

a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;

a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region; and

a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region,

wherein the first region is buried in first groove-like removed portions of the semiconductor region; and

wherein the second region is buried in second groove-like removed portions of the semiconductor region, and provided to oppose at least the channel forming region of the semiconductor region through the first region.

2. The insulated gate semiconductor device as set forth in claim 1 , wherein the second groove-like removed portions of the semiconductor region for the second region have a depth larger than that of the first groove-like removed portions of the semiconductor region for the first region.

3. An insulated gate semiconductor device, comprising:

a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;

a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region; and

a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region,

wherein the second region is positioned between the first region and the semiconductor region so as to be in contact with the first region and the semiconductor region.

4. An insulated gate semiconductor device, comprising:

a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;

a semiconductor region including a channel forming region and an emitter region adjacent to the channel forming region, the semiconductor region being provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region; and

a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region, the second insulating film region being in contact with the semiconductor region, the conductor region being configured so as to have a same voltage as the emitter region,

wherein the insulated gate semiconductor device is an IGBT.

5. The insulated gate semiconductor device as set forth in claim 4 , wherein the second region has the conductor region divided by the second insulating film region.

6. The insulated gate semiconductor device as set forth in claim 4 , wherein a channel in the channel forming region is formed in a vertical direction.

7. The insulated gate semiconductor device as set forth in claim 4 , wherein a channel in the channel forming region is formed in a lateral direction.

8. The insulated gate semiconductor device as set forth in claim 4 , wherein the second insulating film region has a thickness larger than that of the first insulating film region.

9. The insulated gate semiconductor device as set forth in claim 4 , wherein the second region is formed in plural discontinuously in a direction along the gate electrode region.

10. The insulated gate semiconductor device as set forth in claim 4 , wherein the conductor region has a top surface used to be electrically conductive to the emitter region.

11. The insulated gate semiconductor device as set forth in claim 4 , wherein the conductor region is formed of polycrystalline silicon.

12. The insulated gate semiconductor device as set forth in claim 4 , wherein the second insulating film region of the second region is formed of silicon oxide.

13. The insulated gate semiconductor device as set forth in claim 4 , wherein none of the semiconductor region is disposed between the first region and the second region.

14. The insulated gate semiconductor device as set forth in claim 4 , wherein the first insulating film region has portions thereof each having a substantially same thickness and facing with each other through the gate electrode region.