Memory device, programmable resistance memory cell and memory array
View Patent ↗A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices. In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.
1. A memory device comprising:
a substrate;
a patterned first metal layer over said substrate;
a patterned second metal layer over said patterned first metal layer;
a chalcogenide layer over said first metal layer and at least partially surrounding said patterned second metal layer;
an insulating layer at least partially around said chalcogenide layer; and
a patterned third metal layer over said chalcogenide layer.
2. The memory device of claim 1 , wherein said patterned first metal layer comprises elemental tungsten.
3. The memory device of claim 2 , wherein said elemental tungsten is from about 100 Å to about 1000 Å thick.
4. The memory device of claim 1 , wherein said patterned second metal layer comprises elemental silver.
5. The memory device of claim 4 , wherein said elemental silver is from about 175 Å to about 300 Å thick.
6. The memory device of claim 1 , wherein said patterned second metal layer has a cross-sectional area less than an a cross-sectional area of said patterned first metal layer when viewed from above said substrate.
7. The memory device of claim 1 , wherein said patterned second metal layer is formed on said patterned first metal layer.
8. The memory device of claim 1 , wherein said chalcogenide layer is from about 525 Å to about 900 Å thick.
9. The memory device of claim 1 , wherein said chalcogenide layer is a metal-doped chalcogenide layer.
10. The memory device of claim 9 , wherein said metal-doped chalcogenide layer comprises at least a portion of the material comprising the patterned second metal layer.
11. The memory device of claim 1 , wherein said patterned third metal layer is formed on said chalcogenide layer.
12. A programmable resistance memory cell comprising:
a semiconductor substrate;
a first electrode over said semiconductor substrate;
a projecting metal mass over said first electrode, said projecting metal mass having a first thickness relative to its position over said substrate;
a metal-doped chalcogenide layer over said projecting metal mass, said metal-doped chalcogenide layer having a second thickness relative to its position over said substrate at least 20% thicker than the first thickness; and
a second electrode formed over said metal-doped chalcogenide layer.
13. The memory cell of claim 12 , wherein said first electrode comprises elemental tungsten that is from about 100 Å to about 1000 Å A thick.
14. The memory cell of claim 12 , wherein said projecting metal mass comprises elemental silver.
15. The memory cell of claim 12 , wherein said metal-doped chalcogenide layer spans a greater area of said substrate than said first electrode and said projecting metal mass when viewed form above said substrate.
16. The memory cell of claim 12 , wherein said first thickness is from about 175 Å to about 300 Å thick.
17. The memory cell of claim 12 , wherein said metal-doped chalcogenide layer at least partially surrounds said projecting metal mass.
18. The memory cell of claim 12 , wherein said metal-doped chalcogenide layer is in contact with both said projecting metal mass and said first electrode.
19. A resistance variable device comprising:
a first electrode over a semiconductor substrate and at least partially in a first insulating layer;
a chalcogenide layer over said first electrode and at least partially in a second insulating layer;
a metal-comprising layer formed over said first electrode and at least partially within said chalcogenide layer, said metal-comprising layer providing said chalcogenide layer with metal ions; and
a second electrode over the chalcogenide layer and in electrical communication with said first electrode therethrough.
20. The resistance variable device of claim 19 , wherein said chalcogenide layer spans a greater area of said substrate than said first electrode and said metal-comprising layer when viewed from above said substrate.
21. The resistance variable device of claim 19 , wherein said metal-comprising layer comprises silver.
22. The resistance variable device of claim 21 , wherein said metal ions comprise silver ions.
23. The resistance variable device of claim 19 , wherein said first electrode is in contact with said metal-comprising layer and said chalcogenide layer.
24. A resistance variable device comprising:
a bottom electrode over a semiconductor substrate;
a metal-doped chalcogenide layer at least partially on said bottom electrode;
a patterned metal layer at least partially within said metal-doped chalcogenide layer; and
a top electrode formed at least partially on said metal-doped chalcogenide layer.
25. A resistance variable device comprising:
a first electrode and second electrode in electrical communication with each other through a chalcogenide-comprising layer provided between said electrodes; and
metal-comprising layer provided partially within said chalcogenide-comprising layer and in contact with at least one of said first and second electrodes and configured to supply metal ions to said chalcogenide-comprising layer.
26. A memory array comprising a plurality of memory cells, at least some memory cells of said array comprising:
a first electrode;
a metal-doped chalcogenide layer over said first electrode;
a patterned metal layer partially within said metal-doped chalcogenide layer; and
a second electrode over said metal-doped chalcogenide layer.
27. The memory array of claim 26 , wherein said patterned metal layer comprises silver.
28. The memory array of claim 26 , wherein said patterned metal layer is about 175 Å to about 300 Å thick.
29. The memory array of claim 26 , wherein said patterned metal layer spans a smaller area of said substrate than the metal-doped chalcogenide layer when viewed from above said substrate.
30. The memory array of claim 26 , wherein said patterned metal layer spans a smaller area of said substrate than the first electrode when viewed from above said substrate.
31. The memory array of claim 26 , wherein said metal-doped chalcogenide layer is about 525 Å to about 900 Å thick.
32. The memory array of claim 26 , wherein said patterned metal layer is configured so as to provide metal ions to said metal-doped chalcogenide layer.
33. The memory array of claim 26 , wherein said metal-doped chalcogenide layer comprises material from said patterned metal layer.
34. The memory array of claim 26 , wherein at least one of said first and second electrodes is in contact with said metal-doped chalcogenide layer.
35. The memory array of claim 26 , wherein at least one of said first and second electrodes is in contact with said patterned metal layer.