Semiconductor device
View Patent ↗The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109 , a plurality of P-type wells 103 a, 103 b connected to each other via the bottom surface side of the P-type Si substrate 109 , and an N-type well 101 provided so as to surround side portions of the plurality of P-type wells 103 a, 103 b . The semiconductor device also has NMOS transistors 107 a, 107 b provided on the P-type wells 103 a, 103 b , and PMOS transistors 105 a, 105 b, 105 c provided on the N-type well 101 . The semiconductor device still also has an N-type well 133 provided just under the N-type well 101 and connected therewith.
1. A semiconductor device comprising:
an one-conductivity-type semiconductor substrate;
a plurality of one-conductivity-type first regions provided at the element formation surface side of said semiconductor substrate, said plurality of first regions electrically connected with each other via the bottom side of said semiconductor substrate;
a reverse-conductivity-type second region seamlessly provided at the element formation surface side of said semiconductor substrate so as to surround the side portions of each of said plurality of first regions;
a first transistor provided on each of not less than two said first regions, and
a second transistor provided on said second region;
wherein the bottom portion of said second region in said semiconductor substrate is provided at a level of depth, under said element formation surface as a reference level, deeper than the bottom portion of each of said first regions in said semiconductor substrate.
2. The semiconductor device according to claim 1 ,
wherein said second region has a concentration distribution of a reverse-conductivity-type impurity showing a plurality of peaks in the linear direction normal to said element formation surface.
3. The semiconductor device according to claim 1 ,
wherein said second region comprises:
a reverse-conductivity-type upper region provided at a first level of depth, under said element formation surface as a reference level, almost same as that of said first regions in said semiconductor substrate, so as to continuously surround side portions of each of said plurality of first regions; and
a reverse-conductivity-type lower region provided at a second level of depth, under said element formation surface as a reference, deeper than said first regions in said semiconductor substrate, so as to contact with said upper region.
4. The semiconductor device according to claim 3 ,
wherein said lower region is provided on the bottom portion side of a portion of said upper region arranged between said plurality of first regions.
5. The semiconductor device according to claim 3 ,
wherein said lower region is provided on the bottom portion side of said upper region.
6. The semiconductor device according to claim 4 ,
wherein a portion of said lower region projects out just under said first regions.
7. The semiconductor device according to claim 5 ,
wherein a portion of said lower region projects out just under said first regions.
8. The semiconductor device according to claim 3 ,
wherein said lower region is provided on the bottom surface side of a portion of said upper region having said second transistor provided thereon.
9. The semiconductor device according to claim 1 ,
wherein said one conductivity type is P type, and said reverse conductivity type is N type.