Processing system
A processing system on a constructed circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or shared among the group. A star bus couples the group of processing cores and random access memories. Additional layer(s) of star bus may couple many such clusters to each other and to an off-chip environment.
1 . A processing system on a constructed circuit, comprising:
a plurality of processing cores coupled to together; and
a plurality random access memories, each of the plurality of random access memories dedicated to one of the plurality of processing cores.
2 . The system of claim 1 , wherein a first group of the plurality of processing cores are coupled together by a first star bus.
3 . The system of claim 2 , wherein a second group of the plurality of processing cores are coupled together by a second star bus and coupled to the first group of the plurality of processing cores by a third star bus.
4 . The system of claim 2 , further including a shared random access memory coupled to the first star bus.
5 . The system of claim 2 , wherein the first star bus is a unidirectional bus.
6 . The system of claim 1 , wherein one of the plurality of processing cores is disabled when it tests defective.
7 . The system of claim 3 , further including a shared random access memory coupled to the second star bus.
8 . A processing system on a constructed circuit, comprising:
a group of processing cores;
a group of dedicated random access memories, each of the dedicated random access memories directly coupled one of the group of processing cores; and
a star bus coupling the group of processing cores.
9 . The system of claim 8 , further including a shared random access memory coupled to the star bus.
10 . The system of claim 9 , wherein the shared random access memory is interleaved.
11 . The system of claim 8 , further including a second group of processing cores coupled to the group of processing cores by a second star bus.
12 . The system of claim 11 , wherein the second group of processing cores are coupled together by a third star bus.
13 . The system of claim 8 , wherein each of the group of processing cores an isolation system.
14 . The system of claim 8 , wherein the star bus is a unidirectional bus.
15 . A processing system on a constructed circuit, comprising:
a group of processing cores; and
a star bus coupling the group of processing cores.
16 . The system of claim 15 , further including a group of dedicated random access memories, each of the dedicated random access memories directly coupled one of the group of processing cores.
17 . The system of claim 15 , further including a plurality of groups of processing cores coupled to the first group of processing cores by a second star bus.
18 . The system of claim 16 , further including a shared random access memory coupled to the star bus.
19 . The system of claim 18 , wherein the shared random access memory is interleaved.
20 . The system of claim 19 , wherein each of the group of processing cores is fusable.