Apparatus and method for verifying glitch-free operation of a multiplexer

1. A data processing device, comprising:

a circuit;

a plurality of clock signal sources which provide clock signal inputs to the circuit; and

a glitch free verification device coupled to the circuit, wherein the glitch free verification device includes:

a plurality of flip-flops, wherein each flip-flop in the plurality of flip flops receives, as input, a different clock signal from a different one of the plurality of clock signal sources; and

a logic gate coupled to the plurality of flip-flops, wherein each flip-flop in the plurality of flip-flops samples a corresponding clock signal and provides the sampled clock signal to the logic gate, and wherein the logic gate operates on the sampled clock signals from the plurality of flip-flops to verify glitch-free operation of the circuit.

2. The data processing device of claim 1 , wherein each flip-flop in the plurality of flip-flops receives, as input, a different trigger signal, and wherein the flip-flops in the plurality of flip-flops sample their corresponding clock signals when the trigger signal transitions from one state to another.

3. The data processing device of claim 1 , wherein the data processing device is one of an integrated circuit chip, a multi-chip package, a motherboard, a gaming console, a handheld computing device, portable computing device, or non-portable computing device.

4. The data processing device of claim 1 , wherein the logic gate is a NOR gate, and wherein if any of the sampled clock signals from the plurality of flip-flops is at a high state, the NOR gate outputs a signal indicative of non-glitch-free operation.

5. The data processing device of claim 1 , wherein the logic gate is an AND gate, and wherein if any of the sampled clock signals from the plurality of flip-flops is at a low state, the AND gate outputs a signal indicative of non-glitch-free operation.

6. The data processing device of claim 2 , wherein the trigger signals are input to the plurality of flip-flops from a synchronizer that synchronizes output signals from a decoder with the clock signals.

7. The data processing device of claim 6 , wherein the decoder receives at least one clock select signal input from a clock select signal source and generates a plurality of output signals that are provided to the synchronizer as inputs.

8. The data processing device of claim 1 , wherein the circuit is a glitch-free multiplexer.

9. The data processing device of claim 1 , wherein the logic gate outputs a DC signal indicative of either glitch-free or non-glitch-free operation of the circuit.

10. The data processing device of claim 2 , wherein each trigger signal is synchronized to a corresponding clock signal such that the trigger signal transitions only on a falling edge of the corresponding clock signal.

11. The data processing device of claim 2 , wherein each trigger signal is synchronized to a corresponding clock signal such that the trigger signal transitions only on a rising edge of the corresponding clock signal.

12. A glitch-free multiplexer, comprising:

a multiplexer; and

a glitch-free verification device coupled to the multiplexer, wherein:

the multiplexer receives, as input, a plurality of clock signals and a plurality of corresponding trigger signals,

the glitch-free verification device receives the plurality of clock signals and the plurality of corresponding trigger signals, and

the glitch-free verification device determines if the multiplexer is operating in a glitch-free manner based on the plurality of clock signals and the plurality of corresponding trigger signals.

13. The glitch-free multiplexer of claim 12 , wherein the glitch-free verification device comprises:

a plurality of flip-flops, wherein each flip-flop in the plurality of flip flops receives, as input, a different clock signal of the plurality of clock signals; and

a logic gate coupled to the plurality of flip-flops, wherein each flip-flop in the plurality of flip-flops samples a corresponding clock signal and provides the sampled clock signal to the logic gate, and wherein the logic gate operates on the sampled clock signals from the plurality of flip-flops to verify glitch-free operation of the multiplexer.

14. The glitch-free multiplexer of claim 13 , wherein each flip-flop in the plurality of flip-flops receives, as input, a different trigger signal of the plurality of corresponding trigger signals, and wherein the flip-flops in the plurality of flip-flops sample their corresponding clock signals when the trigger signal transitions from one state to another.

15. The glitch-free multiplexer of claim 13 , wherein the flip-flops in the plurality of flip-flops are edge triggered flip-flops.

16. The glitch-free multiplexer of claim 13 , wherein the logic gate is a NOR gate, and wherein if any of the sampled clock signals from the plurality of flip-flops is at a high state, the NOR gate outputs a signal indicative of non-glitch-free operation.

17. The glitch-free multiplexer of claim 13 , wherein the logic gate is an AND gate, and wherein if any of the sampled clock signals from the plurality of flip-flops is at a low state, the AND gate outputs a signal indicative of non-glitch-free operation.

18. The glitch-free multiplexer of claim 12 , further comprising:

a decoder; and

a synchronizer coupled to the decoder, the glitch free verification device, and the multiplexer.

19. The glitch-free multiplexer of claim 13 , further comprising:

a decoder; and

a synchronizer coupled to the decoder, the glitch free verification device, and the multiplexer, wherein the trigger signals are input to the plurality of flip-flops from the synchronizer that synchronizes output signals from the decoder with the clock signals.

20. A method of verifying glitch-free operation of a glitch-free multiplexer, comprising:

receiving a plurality of input clock signals, wherein the input clock signals are inputs to the glitch-free multiplexer;

receiving a plurality of trigger signals, each trigger signal corresponding to a respective one of the plurality of input clock signals;

sampling the plurality of input clock signals based on their corresponding trigger signals in the plurality of trigger signals; and

determining if glitch-free operation of the glitch-free multiplexer is present based on the sampled input clock signals.