Top layers of metal for high performance IC's
View Patent ↗A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1. An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness greater than that of said first dielectric layer and that of said second dielectric layer; and
a second metallization structure over said polymer layer, wherein said second metallization structure comprises a third metal layer over said polymer layer, and said third metal layer has a thickness greater than that of said first metal layer and that of said second metal layer.
2. The integrated circuit chip of claim 1 , wherein said polymer layer comprises polyimide.
3. The integrated circuit chip of claim 1 , wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip.
4. The integrated circuit chip of claim 1 , wherein said passivation layer comprises a topmost CVD-formed insulating layer of said integrated circuit chip.
5. The integrated circuit chip of claim 1 , wherein said second metallization structure comprises a metal trace.
6. The integrated circuit chip of claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).
7. The integrated circuit chip of claim 1 , wherein said second metallization structure comprises copper.
8. The integrated circuit chip of claim 1 , wherein said second metallization structure comprises aluminum.
9. The integrated circuit chip of claim 1 further comprising a solder bump over a contact pad of said first metallization structure, exposed by an opening in said passivation layer.
10. The integrated circuit chip of claim 1 further comprising a solder bump connected to said second metallization structure.
11. The integrated circuit chip of claim 1 further comprising a wirebonding interconnect connected to said second metallization structure.
12. The integrated circuit chip of claim 1 , wherein said polymer layer has a thickness of between 2 and 30 microns.
13. The integrated circuit chip of claim 1 , wherein said second metallization structure is connected to a contact point of said first metallization structure exposed by an opening in said passivation layer, and wherein said contact point has a size within the range of approximately 0.3 microns to 5 microns.
14. The integrated circuit chip of claim 1 , wherein said second metallization structure is connected to a contact point of said first metallization structure exposed by an opening in said passivation layer, and wherein said opening has a diameter in the range of approximately 0.5 microns to 3 microns.