IP Library Granted Patent US 7,351,614
Granted Patent B1
US 7,351,614 · App. 11/230,897 · Granted Apr 1, 2008

Deep trench isolation for thyristor-based semiconductor device

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Quick Facts
Patent No.
US 7,351,614
App. No.
11/230,897
Granted
Apr 1, 2008
Kind
B1
Abstract

A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination. In addition, the single filled trench can further be used to electrically isolate other circuitry, such as conductive shunts to buried circuit nodes in the substrate. These approaches are particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired (e.g., where it is difficult to fill lower portions of the trench with insulative material), and for reducing manufacturing complexity.

Claims (15)

1. A method for manufacturing a thyristor-based semiconductor device having a substrate, a thyristor and a pass device, wherein at least one body region of the thyristor is in the substrate, the method comprising:

removing a portion of the substrate and forming a trench in the substrate and laterally adjacent to said at least one thyristor body region;

forming an insulative material in the trench;

forming conductive filler material in the trench;

masking a first portion of the conductive filler material and etching an unmasked portion of the conductive filler material, thereby forming upper and lower portions of the conductive filler material;

forming an insulative liner material on the etched conductive filler material; and

forming at least two adjacent thyristor control ports in the trench and separated from one another by a portion of the upper conductive filler material, at least one of the thyristor control ports being adapted for capacitively coupling to the thyristor body region in the substrate and for controlling current in the thyristor body, wherein the insulative material and the conductive filler material are configured and arranged to electrically insulate the adjacent thyristor control ports from each other.

2. The method of claim 1 , wherein forming at least two adjacent thyristor control ports includes forming the thyristor control ports over a lower portion of the conductive filler material.

3. The method of claim 2 , wherein forming the thyristor control ports over a lower portion of the conductive filler material includes forming the thyristor control ports on a portion of the insulative liner material formed on the etched conductive filler material.

4. The method of claim 1 , wherein removing a portion of the substrate and forming the trench includes forming a trench having a height:width aspect ratio that is greater than about 2:1.

5. The method of claim 1 , wherein forming conductive filler material in the trench includes recessing the conductive filler material below an upper surface of the substrate, further comprising forming a second insulative material over the recessed conductive filler material and electrically insulating the conductive filler material from circuitry near the upper surface of the substrate.

6. The method of claim 1 , further comprising forming a current shunt extending from a buried circuit region of the thyristor and an upper surface of the substrate.

7. The method of claim 6 , wherein forming an insulative material and forming conductive material in the trench includes forming the insulative material and conductive material such that they electrically insulate the current shunt from said adjacent thyristor control ports.

8. The method of claim 7 , further comprising forming an N well contact extending from an N well region in the substrate to an upper surface of the substrate, wherein forming an insulative material and forming conductive material in the trench includes forming the insulative material and the conductive material such that they electrically insulate the current shunt from the N well contact.

9. The method of claim 1 , further comprising forming an N well contact extending from an N well region in the substrate to an upper surface of the substrate.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2013
From: T-RAM SEMICONDUCTOR, INC.
To: T-RAM (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 031694/0018 →
PURCHASE OPTION AGREEMENT Recorded Jun 3, 2010
From: T-RAM SEMICONDUCTOR, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 024474/0979 →
RELEASE Recorded May 18, 2010
From: SILICON VALLEY BANK
To: T RAM SEMICONDUCTOR INCORPORATED
Reel/Frame 024492/0651 →
SECURITY AGREEMENT Recorded Aug 7, 2008
From: T-RAM SEMICONDUCTOR INCORPORATED
To: SILICON VALLEY BANK
Reel/Frame 021354/0186 →
CURE RECORDATION REF DOC ID NO. 500556640 Recorded Jun 6, 2008
From: T-RAM, INC.
To: T-RAM SEMICONDUCTOR, INC.
Reel/Frame 021062/0404 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2005
From: HORCH, ANDREW
To: T-RAM, INC.
Reel/Frame 017013/0336 →