Random access memory including nanotube switching elements
View Patent ↗A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive nanotube, and a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between a channel electrode and an output node. Input nodes of the first and second inverters are coupled to the set electrodes and the output nodes of the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or in a shadow memory or store mode to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode to transfer the state of the nanotube switching elements to the electronic memory.
1. A memory cell, comprising
a first and second nanotube switching elements, each nanotube switching element including
an output node;
a nanotube channel element having at least one electrically conductive nanotube and a channel electrode;
a control structure having a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said channel electrode and said output node, wherein said channel at least includes said nanotube channel element; and
an electronic memory having cross-coupled first and second inverters wherein an input node of the first inverter is coupled to an output node of the second inverter and an input node of the second inverter is coupled to an output node of the first inverter;
wherein the input node of the first inverter is coupled to the set electrode of the first nanotube switching element and to the output node of the second nanotube switching element; and
wherein the input node of the second inverter is coupled to the set electrode of the second nanotube switching element and to the output node of the first nanotube switching element; and
wherein the channel electrodes are coupled to a channel voltage line.
2. The memory cell of claim 1 wherein the release electrode of the first nanotube switching element is coupled to the release electrode of the second nanotube switching element and wherein both release electrodes are coupled to a release line.
3. The memory cell of claim 1 wherein the first and second inverters are CMOS inverters.
4. The memory cell of claim 1 wherein the first and second nanotube switching elements are non-volatile state devices.
5. The memory cell of claim 1 wherein the first and second nanotube switching elements are fabricated in circuit layers above circuit layers used to fabricate the electronic memory.
6. The memory cell of claim 1 wherein the channel voltage line is set to one-half a supply voltage used by the electronic memory, when the memory cell operates in an electronic memory mode, and wherein the channel voltage line is set to nanotube channel switching voltage, when the circuit operates in an shadow memory mode, wherein the shadow memory mode transfers the state of the electronic memory to the state of the nanotube switching elements.
7. The memory cell of claim 6 wherein the channel voltage line is set to the supply voltage used by the electronic memory, when the memory cell operates in a recall mode, wherein the recall mode transfers the state of the nanotube switching elements to the state of the electronic memory.
8. The memory cell of claim 7 wherein the release electrode of the first nanotube switching element is coupled to the release electrode of the second nanotube switching element and wherein both release electrodes are coupled to a release line, and wherein after the recall mode transfers the state of the nanotube switching elements to the state of the electronic memory the release line is activated to reset the state of the nanotube switching elements.