System, method and apparatus for FEC encoding and decoding
A system, method and apparatus are provided for encoding and decoding a source file. The source file is encoded by dividing it into a plurality of shares comprised of a plurality of packets. A bit vector is generated. For at least one share, an FEC packet is generated by XOR'ing a subset of packets from the plurality of packets in the share in accordance with the bit vector. The process of encoding continues until terminated. Once the FEC encoded packets are received, each of the plurality of packets which is not a linear combination of previously received packets is stored into a file. A sequence of XOR operations to perform in-place on the file to reconstruct the source file are generated and performed on the file.
1. A method for encoding a source file to be transmitted to a receiver, comprising the steps of:
(a) dividing the source file into a plurality of shares comprised of a plurality of packets;
(b) generating a bit vector;
(c) for at least one share, generating an FEC packet by XOR'ing a subset of packets from the plurality of packets in the share in accordance with the bit vector; and
(d) repeating steps (b) and (c).
2. The method according to claim 1 , wherein the bit vector is at least one of a random bit vector and a pseudorandom bit vector.
3. The method according to claim 1 , wherein for two or more shares processed in step (c), the shares are processed in a round-robin fashion and a starting share is randomly selected.
4. The method according to claim 1 , wherein step (d) is repeated for a predetermined time.
5. The method according to claim 1 , wherein step (d) is repeated for a predetermined number of rounds.
6. The method according to claim 1 , wherein step (d) is repeated until a user defined trigger is set.
7. An FEC encoder for encoding a source file to be transmitted to a receiver, comprising:
a packetizer operable to divide the source file into a plurality of shares comprised of a plurality of packets;
a bit vector generator operable to generate a bit vector; and
an encoder operable to, for at least one share, generate an FEC packet by XOR'ing a subset of packets from the plurality of packets in the share in accordance with the bit vector.
8. The FEC encoder according to claim 7 , wherein the bit vector is at least one of a random bit vector and a pseudorandom bit vector.
9. The FEC encoder according to claim 7 , wherein for two or more shares, the encoder processes the shares in a round-robin fashion and a starting share is randomly selected.
10. The FEC encoder according to claim 7 , further comprising:
a timer operable to control how long FEC packets are generated.
11. The FEC encoder according to claim 7 , further comprising:
a counter operable to control how many FEC packets are generated.
12. The FEC encoder according to claim 7 , further comprising:
a triggering unit operable to control how many FEC packets are generated in accordance with a user defined triggering event.
13. An apparatus for encoding a source file to be transmitted to a receiver, comprising:
means for dividing the source file into a plurality of shares comprised of a plurality of packets;
means for generating a bit vector;
means for generating, from at least one share, an FEC packet by XOR'ing a subset of packets from the plurality of packets in the share in accordance with the bit vector; and
means for controlling how long FEC packets are generated.
14. A computer program product comprising a computer usable medium having control logic stored therein for causing a computer to encode a source file to be transmitted to a receiver, said control logic comprising:
first computer readable program code for causing the computer to divide the source file into a plurality of shares comprised of a plurality of packets;
second computer readable program code for causing the computer to generate a bit vector;
third computer readable program code for causing the computer to, for at least one share, generate an FEC packet by XOR'ing a subset of packets from the plurality of packets in the share in accordance with the bit vector; and
fourth computer readable program code for causing the computer to repeat the second and third computer readable program code.
15. The computer program product of claim 14 , wherein the bit vector is at least one of a random bit vector and a pseudorandom bit vector.
16. The computer program product of claim 14 , wherein for two or more shares processed by the third computer readable program code, the third computer readable program code processes the shares in a round-robin fashion and randomly selects a starting share.
17. The computer program product of claim 14 , further comprising:
fifth computer readable program code for causing the computer to repeat the fourth computer readable program code for a predetermined time.
18. The computer program product of claim 14 , further comprising:
fifth computer readable program code for causing the computer to repeat the fourth computer readable program code for a predetermined number of rounds.
19. The computer program product of claim 14 , further comprising:
fifth computer readable program code for causing the computer to repeat the fourth computer readable program code until a user defined trigger is set.