Semiconductor device, wafer and method of designing and manufacturing the same
View Patent ↗A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.
1. A semiconductor device, comprising:
two or more logic blocks in which a plurality of basic cells constituted of a pair of a P-MOS transistor and an N-MOS transistor is regularly aligned such that said basic cells are of a uniform size in the respective logic blocks,
wherein a first interconnect layer includes a narrowest interconnect or a narrowest spacing between interconnects among said plurality of interconnect layers connecting said basic cells in at least one of said logic blocks, and,
wherein, in said logic block in which a cell height of said basic cells is shorter than a spacing between power supply lines in a second interconnect layer provided on said first interconnect layer via an insulating layer, a longitudinal direction of said frequently used interconnect in said first interconnect layer is orthogonal to the cell height direction.
2. The semiconductor device according to claim 1 , wherein a width of said interconnect or a spacing between said interconnects orthogonal to said frequently used interconnect in said first interconnect layer is wider than a width of said frequently used interconnect or a spacing between said frequently used interconnects.
3. The semiconductor device according to claim 1 , wherein a minimum width of said frequently used interconnect is not wider than 0.15 μm, and a minimum spacing between said frequently used interconnects is not wider than 0.15 μm.
4. The semiconductor device according to claim 1 , wherein said minimum spacing between said frequently used interconnects is not more than 0.3 μm.
5. A semiconductor device, comprising:
two or more logic blocks in which a plurality of basic cells constituted of a pair of a P-MOS transistor and an N-MOS transistor is regularly aligned such that said basic cells are of a uniform size in the respective logic blocks,
wherein a first interconnect layer includes a narrowest interconnect or a narrowest spacing between interconnects among said plurality of interconnect layers connecting said basic cells in at least one of said logic blocks, and,
wherein, in said logic block in which a cell height of said basic cells is longer than said spacing between power supply lines in said second interconnect layer provided on said first interconnect layer via said insulating layer, a longitudinal direction of said frequently used interconnect in said first interconnect layer is parallel to the cell height direction.
6. The semiconductor device according to claim 5 , wherein a width of said interconnect or a spacing between said interconnects orthogonal to said frequently used interconnect in said first interconnect layer is wider than a width of said frequently used interconnect or a spacing between said frequently used interconnects.
7. The semiconductor device according to claim 5 , wherein a minimum width of said frequently used interconnect is not wider than 0.15 μm, and a minimum spacing between said frequently used interconnects is not wider than 0.15 μm.
8. The semiconductor device according to claim 5 , wherein said minimum spacing between said frequently used interconnects is not more than 0.3 μm.