Method and system of trace pull test
View Patent ↗The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more accurate. Furthermore, the present invention helps the manufacturer achieve a significant improvement in an IC packaging process.
1. A method of RDL Trace Pull Test for a package, the method comprising following steps:
preparing a die having a plurality of bumps;
coupling a first bias to a first terminal of said die and coupling a second bias to a second terminal of said die to form a circuit loop;
applying an external force to said bumps along substantially a vertical direction;
measuring a strength of said external force when said circuit loop is open;
determining a bonding quality of said die according to said strength; and
selecting good RDL Trace according to said bonding quality.
2. The method of claim 1 , wherein said package comprises a wire-bonding BGA package, a Flip-Chip BGA package, PBGA package, LGA package or a fan-in type and fan-out type wafer level packaging (FO-WLP).
3. The method of claim 1 , wherein said bumps comprise solder balls.
4. The method of claim 1 , wherein said first terminal includes said bumps or UBM (under bump metallurgy) between said bumps and said RDL trace.
5. The method of claim 1 , wherein said second terminal can be UBM (under bump metallurgy) between said RDL trace and a bonding pad.
6. The method of claim 1 , wherein said first bias is electrically positive or electrically negative.
7. The method of claim 1 , wherein said second bias is electrically positive when said first bias is electrically negative electricity, and is electrically negative when said first bias is electrically positive.
8. A method of RDL Trace Pull Test in dimension parameter for a package, the method comprising following steps:
preparing a die having a plurality of bumps;
coupling a first bias to a first terminal of said die and coupling a second bias to a second terminal of said die to form a circuit loop;
applying an external force to said bumps along substantially vertical direction;
measuring a dimension parameter of said bumps when said circuit loop is open;
determining a bonding quality of said die according to said dimension parameter, and
selecting good RDL Trace according to said bonding quality of said die.
9. The method of claim 8 , wherein said package comprises a wire-bonding BGA package, a Flip-Chip BGA package, PBGA package, LGA package or a fan-in type and fan-out type wafer level packaging (FO-WLP).
10. The method of claim 8 , wherein said bumps comprise solder balls.
11. The method of claim 8 , wherein said first terminal includes said bumps or UBM between said bumps and said RDL trace.
12. The method of claim 8 , wherein said second terminal includes UBM between said RDL trace and a bonding pad.
13. The method of claim 8 , wherein said first bias is electrically positive or electrically negative.
14. The method of claim 8 , wherein said second bias is electrically positive when said first bias is electrically negative, and is electrically negative when said first bias is electrically positive.