Field effect transistors with different gate widths
View Patent ↗Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.
1. A semiconductor device comprising:
a first field effect transistor having a first gate insulating film and a first gate electrode composed of polysilicon into which impurities have been introduced; and
a second field effect transistor having a second gate insulating film and a second gate electrode composed of polysilicon into which impurities have been introduced, a gate width of said second field effect transistor being narrower than that of said first field effect transistor, a conduction type of the second field effect transistor coinciding with that of said first field effect transistor, and an impurity concentration in said second gate electrode is lower than the impurity concentration in said first gate electrode,
wherein said first and second gate insulating films have same thickness each other,
wherein the thickness of said first and second gate insulating films is between 0.8 nm and 1.5 nm,
wherein a gate width of said first field effect transistor is equal to or greater than 0.5 μm,
wherein a gate width of said second field effect transistor is equal to or less than 0.5 μm, and
wherein said impurity concentration in said second gate electrode is 60% to 70% of said impurity concentration in said first gate electrode.
2. The semiconductor device according to claim 1 , wherein said impurities introduced into said first and second gate electrodes are phosphorus.
3. The semiconductor device according to claim 1 , wherein said second field effect transistor is an element constituting a memory cell.