Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions, gate insulating films provided on the first and second channel regions, a gate electrode provided on the gate insulating films, and first and second source/drain regions which are located at a distance from each other so as to sandwich the first and second channel regions, the first and second source/drain regions contacting the semiconductor region of the first conductivity type and forming a Schottky junction.
1. A semiconductor device comprising:
a semiconductor substrate; and
a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity type,
the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions of the first conductivity type, gate insulating films provided on the first and second channel regions, a gate electrode provided on the gate insulating films, and first and second source/drain regions which are located at a distance from each other so as to sandwich the first and second channel regions, the first and second source/drain regions contacting the semiconductor region of the first conductivity type and forming a Schottky junction,
wherein the MOS transistor is configured to operate in an accumulation mode.
2. The semiconductor device according to claim 1 ,
wherein the gate electrode includes a first metal semiconductor compound or metal, and the first and second source/drain regions include a second metal semiconductor compound or metal.
3. The semiconductor device according to claim 2 ,
wherein the first metal semiconductor compound is the same material as the second metal semiconductor compound.
4. The semiconductor device according to claim 2 ,
wherein the first metal semiconductor compound or metal is different from the second metal semiconductor compound or metal.
5. The semiconductor device according to claim 2 ,
wherein the semiconductor region of the first conductivity type includes a semiconductor layer in a shape of a rectangular parallelepiped, and the first and second channel regions are located on two side surfaces of the semiconductor layer that are located opposite to each other.
6. The semiconductor device according to claim 2 ,
wherein, in a case where the channel type of the MOS transistor is n-type, a work function of the gate electrode is greater than a mid-gap energy of the semiconductor region of the first conductivity type, and, in a case where the channel type of the MOS transistor is p-type, the work function of the gate electrode is smaller than the mid-gap energy of the semiconductor region of the first conductivity type.
7. The semiconductor device according to claim 6 ,
wherein the semiconductor region of the first conductivity type is a Si region, and the mid-gap energy is 4.6 eV.
8. The semiconductor device according to claim 2 ,
wherein the semiconductor substrate is an SOI substrate.
9. The semiconductor device according to claim 2 ,
wherein, in a case where the channel type of the MOS transistor is p-type, the gate electrode includes RuTa, Ta, Hf—AIN, TaN, Mo (with Ar being ion implanted therein), Ti, or Er, and the first and second source/drain regions include Ru, Ta—AIN, Mo, NiGe, Pt, Ni, or W.
10. The semiconductor device according to claim 2 ,
wherein, in a case where the channel type of the MOS transistor is n-type, the gate electrode includes Ru, Ta—AIN, Mo, NiGe, Pt, Ni, or W, and the first and second source/drain regions include RuTa, Ta, Hf—AIN, TaN, Mo (with Ar being ion implanted therein), Ti, or Er.
11. The semiconductor device according to claim 1 ,
wherein the semiconductor region of the first conductivity type includes a semiconductor layer in a shape of a rectangular parallelepiped, and the first and second channel regions are located on two side surfaces of the semiconductor layer that are located opposite to each other.
12. The semiconductor device according to claim 1 ,
wherein, in a case where the channel type of the MOS transistor is n-type, a work function of the gate electrode is greater than a mid-gap energy of the semiconductor region of the first conductivity type, and, in a case where the channel type of the MOS transistor is p-type, the work function of the gate electrode is smaller than the mid-gap energy of the semiconductor region of the first conductivity type.
13. The semiconductor device according to claim 12 ,
wherein the semiconductor region of the first conductivity type is a Si region, and the mid-gap energy is 4.6 eV.
14. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate is an SOI substrate.
15. The semiconductor device according to claim 1 ,
wherein, in a case where the channel type of the MOS transistor is p-type, the gate electrode includes RuTa, Ta, Hf—AIN, TaN, Mo (with Ar being ion implanted therein), Ti, or Er, and the first and second source/drain regions include Ru, Ta—AIN, Mo, NiGe, Pt, Ni, or W.
16. The semiconductor device according to claim 1 ,
wherein, in a case where the channel type of the MOS transistor is n-type, the gate electrode includes Ru, Ta—AIN, Mo, NiGe, Pt, Ni, or W, and the first and second source/drain regions include RuTa, Ta, Hf—AIN, TaN, Mo (with Ar being ion implanted therein), Ti, or Er.
17. A method of manufacturing a semiconductor device comprising forming a MOS transistor having a channel type of a first conductivity type on a semiconductor substrate,
the forming the MOS transistor comprising:
forming first and second semiconductor regions to be first and second source/drain regions, and a semiconductor region of the first conductivity type including first and second channel regions of the first conductivity type, thereby configuring the MOS transistor to operate in an accumulation mode;
forming a semiconductor film on the first and second channel regions via gate insulating films; and
turning the first and second semiconductor regions and the semiconductor film into metal semiconductor compound regions including metal and semiconductor.
18. The method of manufacturing a semiconductor device according to claim 17 ,
wherein the turning the first and second semiconductor regions and the semiconductor film into the metal semiconductor compound regions including the metal and semiconductor comprises turning the first and second semiconductor regions into a first metal semiconductor compound regions including a first metal and a semiconductor; and turning the semiconductor film into a second metal semiconductor compound region including a second metal which is different from the first metal, and a semiconductor.
19. The method of manufacturing a semiconductor device according to claim 17 ,
wherein the turning the first and second semiconductor regions and the semiconductor film into the metal semiconductor compound regions including the metal and semiconductor comprises turning the first and second semiconductor regions and the semiconductor film into metal semiconductor compound regions including the same metal.
20. A method of manufacturing a semiconductor device comprising forming a MOS transistor having a channel type of a first conductivity type on a semiconductor substrate,
the forming the MOS transistor comprising:
forming first and second semiconductor regions to be first and second source/drain regions, and a semiconductor region of the first conductivity type including first and second channel regions of the first conductivity type, thereby configuring the MOS transistor to operate in an accumulation mode;
forming a semiconductor film on the first and second channel regions via gate insulating films; and
depositing a metal material on the first and second semiconductor regions and a region where the semiconductor film is removed.