System and method for interleaving data in a communication device
View Patent ↗A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. A write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is configured to provide control information, including a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information includes the byte length size of the burst. A read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.
1. A system, comprising:
a memory configured to store a first block of data and a second block of data;
a write module coupled to said memory, said write module configured to write said first block of data to said memory; and
a read module coupled to said memory, said read module configured to read said second block of data from said memory,
wherein said write module is configured to write said first block of data to said memory substantially contemporaneously with said reading of said second block of data from said memory by said read module,
wherein said read module is configured to read said second block of data from said memory substantially contemporaneously with said writing said first block of data to said memory by said write module.
2. The system of claim 1 , wherein said write module is configured to provide a block available signal to said read module indicating that said second block of data is available to be read.
3. The system of claim 2 , wherein said read module is configured to receive said block available signal, wherein said read module reads said second block of data from said memory upon receiving said block available signal.
4. The system of claim 2 , wherein said write module includes a block counter to determine when to provide said block available signal.
5. The system of claim 1 , wherein said write module is coupled to said memory via a first communication path and said read module is coupled to said memory via a second communication path.
6. The system of claim 1 , wherein said read module is configured to access a burst profile bank to determine whether to read said second block of data from said memory in an interleaved fashion.
7. The system of claim 6 , wherein said write module is configured to provide control information to said read module, said control information including a burst profile indicator to indicate said burst profile bank.
8. The system of claim 6 , wherein said write module is configured to provide said control information to said read module by prepending said control information to said first block of data written to said memory.
9. The system of claim 1 , wherein said read module is configured to read said second block of data from said memory in an interleaved fashion.
10. The system of claim 1 , wherein said write module is configured to provide control information to said read module, said control information including an interleave depth of said second block of data, and
wherein said read module is configured to receive said control information and to read said second block of data from said memory in an interleaved fashion in accordance with said interleave depth.
11. The system of claim 10 , wherein said write module is further configured to determine said interleave depth for said second block of data in accordance with a dynamic interleaving algorithm.
12. The system of claim 1 , wherein said write module is configured to receive a burst of data and to generate said first block of data from said burst of data.
13. The system of claim 12 , wherein said write module is configured to receive said burst of data from an forward error correction (FEC) encoder.
14. The system of claim 12 , wherein said write module further includes a FIFO for temporarily storing said burst of data.
15. A system, comprising:
a memory configured to store a first block of data and a second block of data;
a write module coupled to said memory, said write module configured to write said first block of data to said memory; and
a read module coupled to said memory, said read module configured to read said second block of data from said memory, wherein said read module is configured to read said second block of data in an interleaved fashion in accordance with an interleave depth or in a non-interleaved fashion in accordance with a block length,
wherein said write module is configured to write said first block of data to said memory substantially contemporaneously with said reading of said second block of data from said memory by said read module,
wherein said read module is configured to read said second block of data from said memory substantially contemporaneously with said writing said first block of data to said memory by said write module.
16. The system of claim 15 , wherein said write module is configured to provide a block available signal to said read module indicating that said second block of data is available to be read.
17. The system of claim 16 , wherein said read module is configured to receive said block available signal, wherein said read module reads said second block of data from said memory upon receiving said block available signal.
18. The system of claim 16 , wherein said write module includes a block counter to determine when to provide said block available signal.
19. The system of claim 16 , wherein said write module is coupled to said memory via a first communication path and said read module is coupled to said memory via a second communication path.
20. The system of claim 15 , wherein said read module is configured to read said second block of data from said memory and to access a burst profile information to determine if said second block of data should be interleaved.
21. The system of claim 20 , wherein said write module is configured to provide control information to said read module, said control information including a burst profile indicator to indicate said burst profile bank.
22. The system of claim 15 , wherein said write module is configured to provide control information to said read module, said control information including an interleave depth of said second block of data, and
wherein said read module is configured to receive said control information and to read said second block of data from said memory in an interleaved fashion in accordance with said interleave depth.
23. The system of claim 22 , wherein said write module is further configured to determine said interleave depth for said second block of data in accordance with a dynamic interleaving algorithm.
24. The system of claim 21 , wherein said write module is configured to provide said control information to said read module by prepending said control information to said first block of data written to said memory.
25. The system of claim 15 , wherein said write module is configured to receive a burst of data and to generate said first block of data from said burst of data.
26. The system of claim 25 , wherein said write module is configured to receive said burst of data from an forward error correction (FEC) encoder.
27. The system of claim 25 , wherein said write module further includes a FIFO for temporarily storing said burst of data.