Pseudorandom noise lock detector
View Patent ↗A device for detecting data synchronization in data communications includes pseudorandom noise (PN) lock circuits ( 101, 113, 127 ). The PN lock circuits ( 101, 113, 127 ) receive an input data stream ( 109 ). Each of the PN lock circuits ( 101, 113, 127 ) is time offset with respect to the other PN lock circuits. Each of the PN lock circuits ( 101, 113, 127 ) outputs a PN sequence responsive to the input data stream. For each PN lock circuit, there is provided a component ( 105, 117, 131 ) for comparing the PN sequence from the respective PN lock circuit to the input data stream, to determine whether the input data stream and the PN sequence are synchronized. An indication ( 107, 119, 133 ) that the data is synchronized is provided when the input data stream and the PN sequence are synchronized.
1. A device for detecting data synchronization in data communications comprising:
a plurality of pseudorandom noise (PN) lock circuits, each of the PN lock circuits receiving an input data stream, each of the PN lock circuits being time offset with respect to the other PN lock circuits, and each of the PN lock circuits outputting a PN sequence responsive to the input data stream;
for each PN lock circuit, a component for comparing the PN sequence from the respective PN lock circuit to the input data stream, to determine whether the input data stream and the PN sequence are synchronized; and providing an indication that the data is synchronized when the input data stream and the PN sequence are synchronized.
2. The device of claim 1 , wherein the plurality of PN lock circuits operate in parallel on time offset portions of the same input data stream, and the respective components operate on respective time offset portions of the same input data stream.
3. The device of claim 1 , wherein there are provided three PN lock circuits.
4. The device of claim 1 , wherein the time offset corresponds to N/2, wherein the PN sequence is output by the respective PN lock circuit into a shift register, and where N is number of bits of the shift register.
5. The device of claim 1 , wherein the determining by the component for comparing the PN sequence includes staged determinations of whether mutually exclusive portions of the same input data stream and the PN sequence are synchronized.
6. The device of claim 1 , wherein the component for comparing the PN sequence determines that the input data stream and the PN sequence are synchronized when X bits in the input data stream and the PN sequence are the same, where X is more than a majority and less than or equal to the total number of bits.
7. The device of claim 1 , wherein the device for detecting data synchronization is in a circuit connected to a decision feedback equalizer.
8. A device for detecting data synchronization in data communications comprising:
at least one pseudorandom noise (PN) lock component, responsive to a portion of bits in an input PN sequence in an input data stream, outputting a local PN sequence;
at least one comparison component receiving the input data stream and comparing subsets of the local PN sequence to the same input data stream, including at least a first subset and a second subset; the comparing including determining synchronization by whether a predetermined first portion of the bits in the first subset agree with the input data stream and a predetermined second portion of the bits in the second subset agree with the input data stream; and outputting an indication when the data is synchronized, responsive to the at least one comparison component.
9. The device of claim 8 , wherein three PN lock components are provided.
10. The device of claim 8 , wherein the first subset and the second subset are mutually exclusive portions of the same input data stream.
11. The device of claim 8 , wherein the at least one comparison component determines that the bits in the first subset agree when X number of bits in the first subset are the same, and that the bits in the second subset agree when Y number of bits in the second subset are the same, where X and Y each are more than a majority of and less than or equal to the total number of bits being compared in the local PN sequence.
12. The device of claim 8 , wherein the device for detecting data synchronization is in a circuit connected to a decision feedback equalizer.
13. The device of claim 8 , wherein the first subset and the second subset are mutually exclusive portions of the same input data stream.
14. The device of claim 8 , wherein the at least one comparison component determines that the bits in the first or second subset agree when X number of bits in the first or second subset are the same, where X is more than a majority of and less than or equal to the total number of bits being compared in the local PN sequence.
15. The device of claim 8 , wherein the device for detecting data synchronization is in a circuit connected to a decision feedback equalizer.
16. A method for detecting data synchronization in a communication device, comprising:
receiving, at a plurality of pseudorandom noise (PN) lock circuits, an input data stream, each of the PN lock circuits being time offset with respect to the other PN lock circuits, and each of the PN lock circuits outputting a local PN sequence responsive to the input data stream;
for each of the PN lock circuits, performing a staged comparison of the local PN sequence from the respective PN lock circuit to the input data stream, to determine whether the input data stream and the local PN sequence are synchronized; and
providing an indication that the data is synchronized when the input data stream and the local PN sequence are synchronized.
17. The method of claim 16 , wherein the staged comparison includes performing successive comparisons of at least two subsets of mutually exclusive bits of the local PN sequence to the input data stream to determine agreement.
18. The method of claim 17 , wherein there is agreement when at least a majority of the input data stream and a majority of the local PN sequence under comparison agree.
19. The method of claim 16 , wherein the input data stream and the local PN sequence are determined to be synchronized when at least a majority of the input data stream and a majority of the local PN sequence agree.