Comparator circuit with offset control
View Patent ↗A semiconductor integrated circuit has: a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and the common node; a first current supply circuit configured to supply current to the first node; and a second current supply circuit configured to supply current to the second node. A current supply ability of the first current supply circuit is variable.
1. A semiconductor integrated circuit comprising:
a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and said common node;
a first current supply circuit configured to supply current to said first node; and
a second current supply circuit configured to supply current to said second node,
wherein a current supply ability of said first current supply circuit is variable; and
wherein said first current supply circuit includes a plurality of current mirror circuits connected to said first node, and
a number of current mirror circuits of said plurality of current minor circuits which supply current to said first node is changed in accordance with a control signal.
2. A semiconductor integrated circuit comprising:
a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and said common node;
a first current supply circuit configured to supply current to said first node; and
a second current supply circuit configured to supply current to said second node,
wherein a current supply ability of said first current supply circuit is variable; and
wherein said first current supply circuit includes;
a plurality of MOS transistors each of whose drain and gate are connected to said first node; and
a plurality of switches which are connected between a power supply and sources of said plurality of MOS transistors,
wherein said plurality of switches are turned ON in accordance with control signals.
3. The semiconductor integrated circuit according to claim 2 ,
wherein one of said plurality of switches is always turned ON.
4. The semiconductor integrated circuit according to claim 3 ,
wherein said plurality of switches other than said one switch are turned ON one by one in accordance with said control signals.
5. The semiconductor integrated circuit according to claim 4 ,
wherein when only said one switch is turned ON, a current supply ability of said first current supply circuit is lower than a current supply ability of said second current supply circuit, and
when all of said plurality of switches are turned ON, a current supply ability of said first current supply circuit is higher than a current supply ability of said second current supply circuit.
6. The semiconductor integrated circuit according to claim 3 ,
wherein a current supply ability of one of said plurality of MOS transistors connected to said one switch is higher than a current supply ability of any of the others of said plurality of MOS transistors.
7. The semiconductor integrated circuit according to claim 2 ,
wherein said second current supply circuit includes a MOS transistor whose drain, gate and source are connected to said second node, said first node and said power supply, respectively.
8. A semiconductor integrated circuit comprising:
a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and said common node;
a first current supply circuit configured to supply current to said first node; and
a second current supply circuit configured to supply current to said second node,
wherein a current supply ability of said first current supply circuit is variable; and
further comprising a shorting circuit configured to short a gate of said first MOS transistor and a gate of said second MOS transistor when said current supply ability of said first current supply circuit is changed,
wherein said shorting circuit includes a resistance and a switch which are series-connected between said gate of said first MOS transistor and said gate of said second MOS transistor.
9. A method of trimming sensitivity of a comparator,
said comparator having:
a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and second MOS transistor connected between a second node and said common node;
a first current supply circuit configured to supply current to said first node; and
a second current supply, configured to supply current to said second node,
said method comprising:
(A) shorting a gate of said first MOS transistor and a gate of said second MOS transistor;
(B) fixing a current supply ability of said second current supply circuit; and
(C) changing a current supply ability of said first current supply circuit monotonically until an output of said comparator is inverted,
wherein said first current supply circuit includes;
a plurality of MOS transistors each of whose drain and gate are connected to said first node; and
a plurality of switches which are connected between a power supply and sources of said plurality of MOS transistors, one of said plurality of switches being always turned ON,
wherein said (C) changing includes turning ON said plurality of switches other than said one switch one by one.
10. The method according to claim 9 ,
wherein when only said one switch is turned ON, a current supply ability of said first current supply circuit is lower than a current supply ability of said second current supply circuit, and
when all of said plurality of switches are turned ON, a current supply ability of said first current supply circuit is higher than a current supply ability of said second current supply circuit.