Semiconductor integrated circuit having bonding optional function
View Patent ↗Current consumption of an input unit with respect to a bonding option pad is reduced, and erroneous operation of a circuit connected to this bonding option pad is prevented. A boundary scan test circuit is selectively set to an operable or disabled state by a control gate according to a signal from a function set circuit that sets the operation mode according to a potential of a bonding pad. By particularly controlling the operable and disabled state of an input circuit located at the first stage of the test circuit, power consumption can be reduced and erroneous operation while the test circuit is disabled is prevented.
1. A semiconductor integrated circuit comprising:
a pad;
a first transistor for setting said pad to a voltage level of a first logic level in response to application of a power supply voltage to power up said semiconductor integrated circuit;
an inverter for inverting a logic of a potential on said pad; and
a second transistor connected in parallel to said first transistor, and receiving an output signal of said inverter at a control electrode node thereof;
an operation mode of an internal circuit being specified by an output signal of said inverter.
2. The semiconductor integrated circuit according to claim 1 , further comprising a transfer gate inserted between said pad and an input of said inverter, receiving a fixed potential at a control electrode node thereof.
3. The semiconductor integrated circuit according to claim 1 , further comprising a protection circuit coupled to said pad for absorbing an excess voltage higher in absolute value than a first power supply voltage generated at said pad, and wherein
said inverter operates using a second power supply voltage lower in absolute value than said first power supply voltage as an operating power supply voltage.
4. The semiconductor integrated circuit according to claim 3 , further comprising a transfer gate connected between said protection circuit and an input of said inverter and receiving said second power supply voltage at a control gate thereof.
5. The semiconductor integrated circuit according to claim 4 wherein the first and second transistor are connected in parallel between the input of said inverter and a node supplying said second power supply voltage.
6. The semiconductor integrated circuit according to claim 1 , wherein said inverter operates using a first power supply voltage as one operating power supply voltage, and said semiconductor integrated circuit further comprises a level converter for converting an amplitude of the output signal of said inverter to an amplitude of a second power supply voltage higher than the first power supply voltage.
7. The semiconductor integrated circuit according to claim 1 , wherein said paid comprises a bonding option pad.