Interconnect layout method
View Patent ↗In an interconnect layout 100, the first gate pattern, the second gate pattern, the first dummy pattern, and the second dummy pattern are arranged so that, if a wavelength of a light used to expose the first gate pattern and the second gate pattern is λ, natural numbers are m 1 , m 2 , and m 3 , the first predetermined distance is P 1 , the second predetermined distance is P 2 , the third predetermined distance is P 3 , a design value of the first predetermined distance is P 1 ′, a design value of the second predetermined distance is P 2 ′, and a design value of the third predetermined distance is P 3 ′, then the first predetermined distance satisfies relationships of P 1 =m 1 λ and P 1 ′−0.1λ≦P 1 ≦P 1 ′+0.1λ, the second predetermined distance satisfies relationships of P 2 =m 2 λ and P 2 ′−0.1λ≦P 2 ≦P 2 ′+0.1λ, and the third predetermined distance satisfies relationships of P 3 =m 3 λ and P 3 ′−0.1λ≦P 3 ≦P 3 ′+0.1λ.
1. An interconnect layout method for arranging:
a first gate pattern and a second gate pattern provided substantially in parallel to each other at a first predetermined distance between said first gate pattern and said second gate pattern;
a first dummy pattern that is provided adjacent to said first gate pattern on an opposite side to a side on which said second gate pattern is provided, at a second predetermined distance from said first gate pattern in a direction substantially in parallel to a longitudinal direction of said first gate pattern, and that includes no circuitry functions; and
a second dummy pattern that is provided adjacent to said second gate pattern on an opposite side to a side on which said first gate pattern is provided, at a third predetermined distance from said second gate pattern in a direction substantially in parallel to a longitudinal direction of said second gate pattern, and that includes no circuitry functions, wherein
said first gate pattern, said second gate pattern, said first dummy pattern, and said second dummy pattern are arranged so that, if a wavelength of a light used to expose said first gate pattern and said second gate pattern is λ, natural numbers are m 1 , m 2 , and m 3 , the first predetermined distance is P 1 , the second predetermined distance is P 2 , the third predetermined distance is P 3 , a design value of the first predetermined distance is P 1 ′, a design value of the second predetermined distance is P 2 ′, and a design value of the third predetermined distance is P 3 ′, then said first predetermined distance satisfies a relationships of:
P 1 =m 1 λ
P 1 ′−0.1λ≦ P 1 ≦P 1 ′+0.1λ,
said second predetermined distance satisfies relationships of:
P 2 =m 2 λ
P 2 ′−0.1λ≦ P 2 ≦P 2 ′+0.1λ,
and
said third predetermined distance satisfies relationships of:
P 3 =m 3 λ
P 3 ′−0.1λ≦ P 3 ≦P 3 ′+0.1λ.
2. The layout method according to claim 1 , wherein said first gate pattern is electrically connected to said second gate pattern.
3. The layout method according to claim 1 , wherein a relationship of P 1 ′−0.05λ≦P 1 ≦P 1 ′+0.05λ is satisfied.
4. The layout method according to claim 1 , wherein a relationship of P 2 ′−0.05λ≦P 2 ≦P 2 ′+0.05λ is satisfied.
5. The layout method according to claim 1 , wherein a relationship of P 3 ′−0.05λ≦P 3 ≦P 3 ′+0.05λ is satisfied.
6. The layout method according to claim 1 , wherein a relationship of P 1 =P 2 =P 3 is satisfied.
7. The layout method according to claim 1 , wherein said m 1 , said m 2 , and said m 3 are equal to or smaller than 2.
8. The layout method according to claim 1 , wherein
a plurality of blocks each configured by said first gate pattern, said second gate pattern, said first dummy pattern adjacent to said first gate pattern, and said second dummy pattern adjacent to said second gate pattern are arranged,
a third dummy pattern that is provided substantially in parallel to the longitudinal direction of said first gate pattern that constitutes each of said blocks, and that includes no circuitry functions is arranged between said plurality of blocks at a fourth predetermined distance from the each block, and
if said fourth predetermined distance is P 4 and a design value of said fourth predetermined distance is P 4 ′, and a natural number is m 4 , relationships of:
P 4 =m 4 λ
P 4 ′−0.1λ≦ P 4 ≦P 4 ′+0.1λ.
is satisfied.
9. The layout method according to claim 8 , wherein a relationship of P 4 ′−0.05λ≦P 4 ≦P 4 ′+0.05λ is satisfied.
10. The layout method according to claim 8 , wherein said plurality of blocks are not electrically connected to one another.
11. The layout method according to claim 8 , wherein
a relationship of P 1 =P 2 =P 3 =P 4 is satisfied.
12. The layout method according to claim 8 , wherein said m 4 is equal to or smaller than 2.
13. The layout method according to claim 1 , wherein a wavelength of a light used for exposure of said first gate pattern and said second gate pattern is equal to or smaller than 400 nanometers.
14. The layout method according to claim 8 , wherein a wavelength of a light used for exposure of said first gate pattern and said second gate pattern is equal to or smaller than 400 nanometers.
15. The layout method according to claim 1 , wherein a light source of a light used for exposure of said first gate pattern and said second gate pattern is one selected from a group consisting of F 2 , ArF, KrF, and an i-ray.
16. The layout method according to claim 8 , wherein a light source of a light used for exposure of said first gate pattern and said second gate pattern is one selected from a group consisting of F 2 , ArF, KrF, and an i-ray.