IP Library Granted Patent US 7,821,522
Granted Patent B2
US 7,821,522 · App. 11/245,686 · Granted Oct 26, 2010

Image processing apparatus and image display apparatus using same

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,821,522
App. No.
11/245,686
Granted
Oct 26, 2010
Kind
B2
Abstract

An image processing apparatus of the present invention comprising (a) a first signal processing circuit for applying gamma correction to an n-bit (n: a natural number) digital signal inputted as a video signal and for converting the n-bit digital signal into an m-bit (m>n, m: a natural number) digital signal, and (b) a second signal processing circuit for adding a noise signal, which is used for pseudo contour reduction, into the m-bit digital signal from the first signal processing circuit and for outputting a Q-bit (Q: a natural number) digital signal, which is obtained from rounding off a less significant (m−Q) bit (Q≦n) from the m-bit digital signal, to a display section.

Claims (24)

1. An image processing apparatus comprising:

a first signal processing circuit for converting an n-bit (n: a natural number) digital signal inputted as a video signal, into an m-bit (m>n, m: a natural number) digital signal, the n-bit digital signal expressing a tone gradation of 2 n , and the m-bit digital signal expressing a tone gradation of 2 m ; and

a second signal processing circuit having an address counter that is incremented by a horizontal synchronizing signal and a vertical synchronizing signal, the second signal processing circuit for (i) adding a noise signal to the m-bit digital signal converted by the first signal processing circuit, (ii) rounding down a less significant (m−Q) bit (Q<n, Q: a natural number) from the m-bit digital signal having added thereto the noise signal, and (iii) outputting the resulting Q-bit digital signal,

the first signal processing circuit including at least one look-up table for converting the inputted n-bit digital signal to the m-bit digital signal,

the first signal processing circuit converting the n-bit digital signal expressing the tone gradation of 2 n to the m-bit digital signal expressing the tone gradation of 2 m , by changing between, per display region, a plurality of look-up tables in which various values are entered in advance,

wherein the noise signal is added to the video signal based on a value of the address counter.

2. The image processing apparatus as set forth in claim 1 , wherein:

an average value of a signal level of the noise signal is set to zero.

3. The image processing apparatus as set forth in claim 1 , wherein:

the noise signal is a random noise signal with no regularity in its cycle of amplitude.

4. The image processing apparatus as set forth in claim 1 , wherein:

the noise signal is stored in a noise memory, the noise memory storing the noise signal for one screen.

5. The image processing apparatus as set forth in claim 1 , wherein:

the noise signal is stored in a noise memory, the noise memory storing the noise signal per block units smaller than one screen.

6. The image processing apparatus as set forth in claim 5 , wherein:

the noise signal is a signal generated by using an arbitrary noise pattern table and altering a starting point of the noise pattern for each of the block units.

7. The image processing apparatus as set forth in claim 1 , wherein:

a histogram of an amplitude of the noise signal shows Gaussian distribution where zero amplitude of the noise signal is at the center.

8. An image processing apparatus comprising:

a first signal processing circuit for converting an n-bit (n: a natural number) digital signal inputted as a video signal, into an m-bit (m>n, m: a natural number) digital signal, the n-bit digital signal expressing a tone gradation of 2 n , and the m-bit digital signal expressing a tone gradation of 2 m ; and

a second signal processing circuit having an address counter that is incremented by a horizontal synchronizing signal and a vertical synchronizing signal, the second signal processing circuit for (i) adding a noise signal to the m-bit digital signal converted by the first signal processing circuit, (ii) rounding down a less significant (m−Q) bit (Q<=n, Q: a natural number) from the m-bit digital signal having added thereto the noise signal, and (iii) outputting the resulting Q-bit digital signal,

the first signal processing circuit including at least one look-up table for converting the inputted n-bit digital signal to the m-bit digital signal,

the first signal processing circuit converting the n-bit digital signal expressing the tone gradation of 2 n to the m-bit digital signal expressing the tone gradation of 2 m , by rewriting, per display region, values in the look up table,

wherein the noise signal is added to the video signal based on a value of the address counter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2017
From: SHARP CORPORATION
To: III HOLDINGS 10, LLC
Reel/Frame 042000/0258 →
Priority Claims (2)
JP 2000-84663 · Mar 24, 2000 · national
JP 2001-13864 · Jan 22, 2001 · national
Continuity (2)
Continuation 0981559400 · Mar 23, 2001
Related Publication 20060028484A1 · Feb 9, 2006