Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module
A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.
1. A semiconductor module having an internal semiconductor chip stack on a wiring substrate, the semiconductor chip stack comprising:
semiconductor chips which are stacked on top of one another and comprise a top semiconductor chip and at least one bottom semiconductor chip, the semiconductor chips having, on their active top side, an additional wiring structure with a metal coating, which comprises a plurality of metal layers, and with interconnects between contact areas in a central region and bonding connection pads in edge regions, the wiring structure configuring originally identical semiconductor chips in such a manner that the contact areas which were originally arranged centrally in the central region are rewired to bonding connection pads in edge regions, and the bonding connection pads being electrically connected to the wiring substrate via bonding connections, and the semiconductor chips being stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them.
2. The semiconductor module of claim 1 , comprising wherein the contact areas are arranged in at least one row, the interconnects extending from these contact areas to one of the edge regions of the semiconductor chip and merging into the bonding connection pads there.
3. The semiconductor module of claim 1 , comprising wherein the semiconductor chip stack having the bonding connections to the semiconductor chips is embedded in a plastic housing composition.
4. The semiconductor module of claim 1 , comprising wherein the semiconductor chips are stacked on top of one another and configured such that they are offset on one side, and an individual edge region of the top side of the respective semiconductor chip comprises bonding connection pads.
5. The semiconductor module of claim 1 , comprising wherein the semiconductor chips are stacked on top of one another such that they are offset on alternate sides, and an individual edge region of the top side of the respective semiconductor chip comprises bonding connection pads.
6. The semiconductor module of claim 1 , wherein the semiconductor chips are stacked on top of one another such that they are diagonally offset, and two edge regions which are arranged at an angle to one another of the top side of the respective semiconductor chip comprise bonding connection pads.
7. The semiconductor module of claim 1 , wherein the wiring substrate comprises, on its top side, a wiring structure which leads to external contacts on the underside of the wiring substrate via interconnects of differing length within the wiring substrate and thus compensates for the different lengths of the bonding connections to the stacked semiconductor chips which are arranged such that they are offset on alternate sides.
8. The semiconductor module of claim 1 , comprising wherein the internal semiconductor chip stack comprises memory components, having storage capacities in the region of several gigabits and a data rate transfer range of several hundred megahertz.
9. The semiconductor module of claim 1 , comprising wherein the internal semiconductor chip stack comprises at least one logic chip, preferably a microprocessor.