Method for making a passivated semiconductor substrate
The present invention is related to a method for making a passivated semiconductor substrate comprising the steps of providing a substrate surface comprising or consisting of mono-crystalline semiconductor material other than silicon and forming a silicon layer on the substrate surface, such that the silicon layer is substantially lattice matched to the mono-crystalline semiconductor material. It is also related to a semiconductor substrate passivated according to the method.
1 . A method for making a passivated semiconductor substrate, comprising the steps of:
providing a substrate surface comprising a mono-crystalline semiconductor material other than silicon; and
forming a silicon layer on the substrate surface, such that the silicon layer is substantially lattice matched to said mono-crystalline semiconductor material.
2 . A method according to claim 1 , wherein the mono-crystalline semiconductor material is selected from the group consisting of Ge, GaAs, and combinations thereof.
3 . A method according to claim 1 , wherein the silicon layer passivates the substrate surface in relation to a subsequent IC processing step.
4 . A method according to claim 1 , further comprising conducting at least one subsequent IC processing step, wherein a thickness of the silicon layer is selected such that during and after the subsequent IC processing step the silicon layer passivates the substrate surface in relation to a further IC processing step.
5 . A method according to claim 1 , further comprising conducting at least one subsequent IC processing step, wherein after the subsequent IC processing step the thickness of the silicon layer is from 1 to 6 monolayers.
6 . A method according to claim 1 , further comprising conducting at least one subsequent IC processing step, wherein after the subsequent IC processing step the thickness of the silicon layer is from 1 to 4 monolayers.
7 . A method according to claim 1 , further comprising conducting at least one subsequent IC processing step, wherein after the subsequent IC processing step the thickness of the silicon layer is from 1 to 2 monolayers.
8 . A method according to claim 1 , further comprising conducting at least one subsequent IC processing step, wherein after the subsequent IC processing step the thickness of the silicon layer is 1 monolayer.
9 . A method according to claim 3 , wherein the subsequent IC processing step comprises at least one step selected from the group consisting of oxidation of a part of the silicon layer, formation of a dielectric layer stack, and formation of a gate stack.
10 . A method according to claim 1 , further comprising a step of rendering the semiconductor substrate surface substantially free of an oxide before the step of forming a silicon layer.
11 . A method according to claim 1 , wherein the silicon layer is formed by epitaxial growth.
12 . A method according to claim 11 , wherein at least one silicon precursor selected from the group consisting of silane, dichlorosilane, trisilane, and combinations thereof is used during epitaxial growth.
13 . A method according to claim 11 , wherein N 2 is used as carrier gas during epitaxial growth.
14 . A method according to claim 11 , wherein a trisilane silicon precursor and a N 2 carrier gas are used during epitaxial growth.
15 . A passivated semiconductor substrate prepared according to the method of claim 1 .
16 . A passivated semiconductor substrate according to claim 13 , having an Omhic current-voltage profile which can be measured by a spreading resistance analysis technique.
17 . Use of a passivated semiconductor substrate according to claim 13 in a semiconductor device.