IP Library Granted Patent US 7,185,149
Granted Patent B2
US 7,185,149 · App. 11/250,443 · Granted Feb 27, 2007

Selective storage in a cache memory device

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Quick Facts
Patent No.
US 7,185,149
App. No.
11/250,443
Granted
Feb 27, 2007
Kind
B2
Abstract

A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predetermined attribute.

Claims (6)

1. An apparatus, comprising:

an I/O unit transferring a reception data including a header and a communication data;

a main memory; and

a cache memory device having a cache section and a control section and being connected between said I/O unit and said main memory, said control section of said cache memory device controlling to store said header of said reception data in said cache section and to store said communication data of said reception data in said main memory,

wherein said I/O unit comprises an attribute adding section that affixes a first attribute information to said header and affixes a second attribute information to said communication data.

2. The apparatus according to claim 1 , wherein said cache memory device stores said header in said cache section when an attribute information affixed to said header comprises said first attribute information and stores said communication data in said main memory when the attribute information affixed to said communication data comprises said second attribute information.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 11, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025346/0877 →