ESD protection devices with SCR structures for semiconductor integrated circuits
View Patent ↗To control the uneven distribution of current density and reduce the area of an ESD protection circuit in an SCR-type ESD protection device. An N-type well 11 , and P-type wells 12 a and 12 b disposed oppositely and adjacent to the N-type well 11 , with the N-type well 11 interposed between them, are formed on the surface of a semiconductor substrate. A high concentration N-type region 15 a is formed on the surface of the P-type well 12 a , a high concentration N-type region 15 b is formed on the surface of the P-type well 12 b , and each of them is grounded. Further, a high concentration P-type region 14 a is formed, oppositely to the high concentration N-type region 15 a , on the surface of the N-type well 11 , and a high concentration P-type region 14 b is formed, oppositely to the high concentration N-type region 15 b , on the surface of the N-type well 11 , and each of them is connected to an I/O pad. A high concentration N-type region 13 is formed on the N-type well 11 , being interposed between the high concentration P-type region 14 a and the high concentration P-type region 14 b , and connected to a trigger device. A surge loaded on the I/O pad is released to the ground terminal via the SCR structures on the both sides.
1. A semiconductor integrated device comprising an electrostatic discharge ESD protection circuit constituted on a semiconductor substrate, wherein
said ESD protection circuit comprises:
a first-conductivity type well formed on a surface of said semiconductor substrate;
a first second-conductivity type well and a second second-conductivity type well formed oppositely to each other and adjacent to said first-conductivity type well, with said first-conductivity type well interposed between them, on the surface of said semiconductor substrate;
a first high concentration first-conductivity type region formed on the surface of said first second-conductivity type well;
a second high concentration first-conductivity type region formed on the surface of said second second-conductivity type well;
a first high concentration second-conductivity type region formed oppositely to said first high concentration first-conductivity type region on the surface of said first-conductivity type well;
a second high concentration second-conductivity type region formed oppositely to said second high concentration first-conductivity type region on the surface of said first-conductivity type well;
a third high concentration first-conductivity type region formed on the surface of said first-conductivity type well and interposed between said first high concentration second-conductivity type region and said second high concentration second-conductivity type region; and
a trigger device having two terminals, wherein a current flows when a voltage higher than a predetermined value is applied across said two terminals;
said first high concentration second-conductivity type region and said second high concentration second-conductivity type region are connected to an I/O pad;
one of the terminals of said trigger device is connected to said third high concentration first-conductivity type region via wiring and the other terminal is connected to a reference voltage terminal; and
said first high concentration first-conductivity type region and said second high concentration first-conductivity type region are connected to said reference voltage terminal.
2. The semiconductor integrated device as defined in claim 1 wherein only said third high concentration first-conductivity type region exists between said first high concentration second-conductivity type region and said second high concentration second-conductivity type region on said first-conductivity type well.
3. The semiconductor integrated device as defined in claim 1 wherein the shape of said first high concentration first-conductivity type region, said second high concentration first-conductivity type region, said first high concentration second-conductivity type region, and said second high concentration second-conductivity type region is rectangular looking from the direction perpendicular to the surface of said semiconductor substrate, and the rectangles are parallel to each other in the long direction.
4. The semiconductor integrated device as defined in claim 3 wherein said rectangles have approximately the same length in the long direction.
5. The semiconductor integrated device as defined in claim 4 wherein said length in the long direction is 10 μm to 50 μm.
6. The semiconductor integrated device as defined in claim 3 wherein said third high concentration first-conductivity type region is formed so that the long direction of said third high concentration first-conductivity type region is parallel to the long direction of said rectangles.
7. The semiconductor integrated device as defined in claim 6 wherein connection regions for wiring one of said trigger device are provided the both ends of said third high concentration first-conductivity type region in the long direction.
8. The semiconductor integrated device as defined in claim 1 wherein, with said third high concentration first-conductivity type region as a center, said first high concentration second-conductivity type region is structured symmetrically to said second high concentration second-conductivity type region, and said first high concentration first-conductivity type region is structured symmetrically to said second high concentration first-conductivity type region.
9. The semiconductor integrated device as defined in claim 1 wherein said first second-conductivity type well and said second second-conductivity type well are formed commonly surrounding said first-conductivity type well.
10. The semiconductor integrated device as defined in claim 1 wherein said first high concentration first-conductivity type region, said second high concentration first-conductivity type region, said first high concentration second-conductivity type region, said second high concentration second-conductivity type region, and said third high concentration first-conductivity type region are connected to a first wiring group within a first metal wiring layer formed above the surface of said semiconductor substrate, with an insulator interposed between them, via a plurality of contact holes, respectively,
said first wiring group is connected to a second wiring group within a second metal wiring layer formed above said first metal wiring layer, with another insulator interposed between them, via a plurality of through holes, and wirings included in said second wiring group are wired in the direction perpendicular to said long direction at connection points of said through holes.
11. The semiconductor integrated device as defined in claim 10 wherein a third wiring group included in said second wiring group connected to said first high concentration first-conductivity type region, said second high concentration first-conductivity type region, said first high concentration second-conductivity type region, and said second high concentration second-conductivity type region is provided in a region above said first high concentration first-conductivity type region, said second high concentration first-conductivity type region, said first high concentration second-conductivity type region, and said second high concentration second-conductivity type region, and
wirings included in said second wiring group connected to said third high concentration first-conductivity type region are disposed at least one of the both ends of said third wiring group.