Semiconductor device having an SOI structure, manufacturing method thereof, and memory circuit
View Patent ↗The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.
1. A semiconductor device having an SOI structure, comprising:
a silicon substrate;
a buried insulating layer which is formed on said silicon substrate; and
a semiconductor layer which is formed on said buried insulating layer, wherein
said semiconductor layer includes a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type,
a gate electrode is formed on said body region between said source region and said drain region via a gate oxide film,
said source region includes an extension layer of the second conduction type, said semiconductor layer being between the bottom surface of said extension layer and said buried insulating layer, and a silicide layer on top of said extension layer wherein the upper surface of said silicide layer is higher than the upper surface of said gate oxide film and the bottom surface of said silicide layer is higher than the upper surface of said body region between said source region and said drain region,
said silicide layer is electrically connected to said body region via a diffusion layer of the first conduction type formed in said semiconductor layer, the diffusion layer extending entirely from one end of said source region to another end in a channel width direction,
said drain region includes a drain diffusion region in contact with said buried insulating layer, and an extension layer of the second conduction type arranged not to reach said buried insulating layer, and
said first conduction type and said second conduction type are different from each other.
2. The semiconductor device of claim 1 , wherein
said extension layer is higher in effective concentration of impurities of the second conduction type as compared with an extension layer formed on said drain region.
3. A memory circuit comprising:
an access transistor which is connected between a bit line and a storage node;
a load transistor which is connected between a power supply and said storage node; and
a driver transistor which is connected between a GND and said storage node,
wherein each of said load transistor and said driver has the semiconductor structure as recited in claim 1 .