IP Library Patent Application 11253490
Patent Application
App. No. 11/253,490

Attachment of integrated circuit structures and other substrates to substrates with vias

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Quick Facts
Patent No.
US None
App. No.
11/253,490
Abstract

Vias ( 210, 210 B) are formed in a surface of a substrate. At least portions of contact pads ( 139, 350 ) are located in the vias. Contact pads ( 150, 340 ) of an integrated circuit structure are inserted into the vias and attached to the contact pads ( 139, 350 ) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad ( 350 ) in the substrate but also a surrounding region. Solder ( 930 ) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers ( 910.1, 910.2 ), with the top layer ( 910.2 ) being more solder wettable than the bottom layer ( 910.1 ) and the top layer covering only a portion of the bottom layer.

Claims (41)

1 . A structure comprising:

(1) a first integrated circuit structure comprising:

a semiconductor substrate;

one or more first conductive contact pads protruding out at a surface of the first integrated circuit structure;

(2) a first substrate comprising a circuit which comprises one or more first conductive contact pads, wherein at least a portion of each of the one or more first contact pads of the first substrate is located in a corresponding via in a surface of the first substrate;

wherein the protruding first contact pads of the first integrated circuit structure are inserted into the corresponding vias of the first substrate and attached to the first contact pads of the first substrate;

wherein each first contact pad of the first integrated circuit structure has a non-solder portion inside the corresponding via.

2 . The structure of claim 1 wherein the first contact pads of the first integrated circuit structure are attached to the first contact pads of the first substrate with solder.

3 . The structure of claim 1 wherein the first contact pads of the first integrated circuit structure are attached to the first contact pads of the first substrate without solder with thermal or thermosonic compression.

4 . The structure of claim 1 wherein the non-solder portions of the protruding first contact pads of the first integrated circuit structure are made of copper and/or gold and/or nickel.

5 . The structure of claim 1 wherein the first substrate comprises a semiconductor substrate.

6 . The structure of claim 1 wherein the first substrate is an integrated circuit packaging substrate which does not comprise a semiconductor substrate.

7 . The structure of claim 1 wherein the first substrate is a printed circuit board.

8 . The structure of claim 1 wherein a spacing between the bottom surface of the semiconductor substrate and the top surface of the first substrate is at least 5 μm.

9 . The structure of claim 1 wherein at least a portion of the bottom surface of the semiconductor substrate is not covered by any dielectric layer in the first integrated circuit structure.

10 . The structure of claim 1 wherein at least a portion of the bottom surface of the semiconductor substrate is covered by a dielectric in the first integrated circuit structure.

11 . The structure of claim 1 wherein at least 10 μm of each protruding first contact pad is inside the corresponding via.

12 . The structure of claim 1 wherein the first integrated circuit structure is an interposer that comprises no transistors and no diodes.

13 . The structure of claim 1 wherein the first integrated circuit structure comprises a transistor or a diode, the transistor or the diode having a semiconductor region in the semiconductor substrate.

14 . The structure of claim 1 wherein each first contact pad of the first substrate covers a bottom and sidewalls of the corresponding via.

15 . The structure of claim 1 further comprising:

(4) a second integrated circuit structure comprising:

a semiconductor substrate;

one or more first conductive contact pads protruding out at a surface of the second integrated circuit structure;

wherein the first integrated circuit structure further comprises one or more second conductive contact pads, wherein at least a portion of each of the one or more second contact pads of the first integrated circuit structure is located in a corresponding via in a surface of the first integrated circuit structure;

wherein the protruding first contact pads of the second integrated circuit structure are inserted into the corresponding vias of the first integrated circuit structure and attached to the second contact pads of the first integrated circuit structure;

wherein each first contact pad of the second integrated circuit structure has a non-solder portion inside the corresponding via of the first integrated circuit structure.

16 . The structure of claim 1 wherein the first contact pads of the first integrated circuit structure are located on a first side of the first integrated circuit structure, and the second contact pads of the first integrated circuit structure are located on a second side of the first integrated circuit structure, the first side being opposite to the first side.

17 . The structure of claim 1 wherein each first contact pad of the first integrated circuit structure is provided by a conductor formed in a corresponding through via in the semiconductor substrate and protruding out of the through via.

18 . The structure of claim 17 wherein the first contact pads of the first integrated circuit structure protrude out at the surface which is opposite to an active surface of the first integrated circuit structure.

19 . A first substrate comprising:

one or more conductive contact pads for attachment to circuitry; and

a dielectric having one or more openings over the one or more contact pads;

wherein a surface of at least one of the openings has a first portion which is a surface portion of one of the contact pads, and a second portion made from a different material than the first portion.

20 . The first substrate of claim 19 wherein the second portion of the bottom of said one of the openings is less solder wettable than the first portion.

21 . The first substrate of claim 19 wherein the second portion is dielectric.

22 . The first substrate of claim 19 in combination with solder at least on the first portion.

23 . The first substrate of claim 19 in combination with a second substrate having a contact pad soldered to said one of the contact pads of the first substrate with solder on the first portion.

24 . The combination of claim 23 wherein the second substrate is a semiconductor integrated circuit.

25 . The first substrate of claim 19 wherein the first substrate is a semiconductor integrated circuit packaging substrate that does not include a semiconductor substrate.

26 . The first substrate of claim 19 wherein the firs substrate is a semiconductor integrated circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2012
From: ALLVIA, INC.
To: INVENSAS CORPORATION
Reel/Frame 027873/0022 →