Detection of the zero crossing of an A.C. voltage

1. A circuit for detecting a zero crossing of a variable voltage across at least one switching element, comprising:

first means of hysteresis comparison of the voltage across the switching element with two first respectively high and low values according to whether the voltage increases or decreases;

second means for comparing the voltage across the switching element with a second value ranging between the first two thresholds;

third means for comparing the voltage across the switching element with a third value smaller than the first low value; and

a logic analysis element of the results of said means for comparing having an output providing the zero crossing detection result if the slope of said voltage is comprised within a range of values.

2. The circuit of claim 1 , wherein a slope measurement is initialized by the passing under at least one value by a decrease in said voltage.

3. The circuit of claim 1 , wherein the logic analysis element comprises:

first controllable means of XOR-type combination of the results of the first two comparison means;

second controllable means of XOR-type combination of the results of the last two comparison means; and

two delay means of fixed time constants, triggered either by the respective crossings of the second and third values by a decrease in the voltage either by an edge in a given direction of the second and third comparison means, respectively, and for respectively controlling the first and second combination means, the result of the detection being provided by the output of the first combination means.

4. The circuit of claim 3 , wherein:

the first delay means are reset by an active output of the second combination means; and

the second delay means are reset by an active output of the first combination means.

5. The circuit of claim 4 , wherein the combination and delay means are formed of flip-flops.

6. A method for detecting a zero crossing of a variable voltage across at least one switching element, comprising:

comparing the voltage across the switching element with two first respectively high and low values according to whether the voltage increases or decreases;

comparing the voltage across the switching element with a second value ranging between the first two thresholds;

comparing the voltage across the switching element with a third value smaller than the first low value; and

analyzing with a logic the results of said former comparisons for providing the zero crossing detection result.

7. A circuit for detecting a zero crossing of a variable voltage across at least one switching element, comprising:

a first hysteresis comparison circuit that compares the voltage across the switching element with two first respectively high and low values according to whether the voltage increases or decreases;

a second comparison circuit that compares the voltage across the switching element with a second value ranging between the first two thresholds;

a third comparison circuit that compares the voltage across the switching element with a third value smaller than the first low value; and

a logic circuit, responsive to the first hystersis comparison circuit, the second comparison circuit, and the third comparison circuit that provides a zero crossing detection result if the slope of said voltage is comprised within a range of values.

8. The circuit of claim 7 , wherein a slope measurement is initialized by the passing under at least one value by a decrease in said voltage.

9. The circuit of claim 7 , wherein the logic analysis circuit comprises:

a first controllable XOR-type combination circuit of the results of the first hysteresis comparison circuit and the second comparison circuit;

a second controllable XOR-type combination circuit of the results of the second comparison circuit and the third comparison circuit; and

two delay circuits having fixed time constants, triggered either by the respective crossings of the second and third values by a decrease in the voltage either by an edge in a given direction of the second and third comparison circuits, respectively, and for respectively controlling the first and second XOR-type combination circuits, the result of the detection being provided by the output of the first XOR-type combination circuit.

10. The circuit of claim 9 , wherein:

one of the delay circuits are reset by an active output of the second combination means; and

another of the delay circuits are reset by an active output of the first combination means.

11. The circuit of claim 10 , wherein the combination and delay circuits are formed of flip-flops.