IP Library Granted Patent US 7,439,171
Granted Patent B2
US 7,439,171 · App. 11/256,147 · Granted Oct 21, 2008

Method for manufacturing electronic device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,439,171
App. No.
11/256,147
Granted
Oct 21, 2008
Kind
B2
Abstract

A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The method includes: forming a via hole in the interlayer insulating film; forming a resin film, plugging the via hole, on the interlayer insulating film; forming a resist mask having an opening for an interconnect on the interlayer insulating film; and etching the interlayer insulating film through an etching mask of the resist mask to form a trench for the interconnect connected with the via hole. The resin film is being capable of trapping a basic substance.

Claims (37)

1. A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and said via hole and the trench for the interconnect are plugged with an electric conductor film, comprising:

forming a via hole in said interlayer insulating film;

forming a resin film on said interlayer insulating film, said resin film plugging said via hole, and being capable of trapping a basic substance;

forming a resist mask having an opening for an interconnect on said interlayer insulating film; and

etching said interlayer insulating film through said resist mask to form a trench for said interconnect, said trench being connected with said via hole, wherein an acidic agent is added to said resin film.

2. The method according to claim 1 , further comprising forming a dummy plug composed of said resin film in said via hole by etching a portion of said resin film exposed outside said via hole off before said forming the resist mask, wherein, in said forming the resist mask, said resist mask is formed on said dummy plug and on said interlayer insulating film.

3. The method according to claim 1 , wherein a resist mask having an opening for an interconnect is formed on said resin film in said forming the resist mask, and wherein said resin film and said interlayer insulating film are dry-etched through an etching mask of said resist mask in said forming the trench for the interconnect.

4. The method according to claim 1 , wherein said resin film includes cellulose.

5. The method according to claim 2 , wherein said resin film includes cellulose.

6. The method according to claim 3 , wherein said resin film includes cellulose.

7. A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and said via hole and the trench for the interconnect are plugged with an electric conductor film, comprising:

forming an etch stop layer on said substrate;

forming said interlayer insulating film on said etch stop layer;

forming a via hole in said interlayer insulating film;

forming a resin film on said interlayer insulating film, said resin film plugging said via hole, and containing cellulose;

forming a resist mask having an opening for an interconnect on said interlayer insulating film;

etching said interlayer insulating film through said resist mask to form a trench for said interconnect, said trench being connected with said via hole;

removing said resist mask and said resin film using a first process; and

removing said etch stop layer using a second process different from said first process.

8. The method according to claim 7 , further comprising forming a dummy plug composed of said resin film in said via hole by etching a portion of said resin film exposed outside said via hole off before said forming the resist mask, wherein, in said forming the resist mask, said resist mask is formed on said dummy plug and on said interlayer insulating film.

9. The method according to claim 7 , wherein a resist mask having an opening for an interconnect is formed on said resin film in said forming the resist mask, and wherein said resin film and said interlayer insulating film are dry-etched through an etching mask of said resist mask in said forming the trench for the interconnect.

10. The method according to claim 4 , further comprising thermally processing said resin film within an inert gas or hydrogen gas after forming said resin film to carbonize at least a portion thereof.

11. The method according to claim 7 , further comprising thermally processing said resin film within an inert gas or hydrogen gas after forming said resin film to carbonize at least a portion thereof.

12. A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and said via hole and the trench for the interconnect are plugged with an electric conductor film, comprising:

forming a via hole in said interlayer insulating film;

forming a resin film on said interlayer insulating film, said resin film plugging said via hole, and containing cellulose;

thermally processing said resin film within an inert gas or hydrogen gas after forming said resin film to carbonize at least a portion thereof;

forming a dummy plug composed of said resin film in said via hole by etching a portion of said resin film exposed outside said via hole;

forming a resist mask having an opening for an interconnect on said interlayer insulating film, said resist mask is formed on said dummy plug and on said interlayer insulating film; and

etching said interlayer insulating film through said resist mask to form a trench for said interconnect, said trench being connected with said via hole.

13. The method according to claim 9 , further comprising thermally processing said resin film within an inert gas or hydrogen gas after forming said resin film to carbonize at least a portion thereof.

14. The method according to claim 7 , wherein an acidic agent is added to said resin film.

15. The method according to claim 1 , wherein said resin film is removed by conducting a dry etching process employing an active hydrogen species that is composed of hydrogen plasma or hydrogen radical as an etching gas in said forming the dummy plug.

16. The method according to claim 7 , wherein said resin film is removed by conducting a dry etching process employing an active hydrogen species that is composed of hydrogen plasma or hydrogen radical as an etching gas in said forming the dummy plug.

17. The method according to claim 1 , further comprising forming an anti-reflection film on said interlayer insulating film before said forming the resist mask,

wherein said resist mask is formed on said anti-reflection film in said forming said resist mask.

18. The method according to claim 7 , further comprising forming an anti-reflection film on said interlayer insulating film before said forming the resist mask, wherein said resist mask is formed on said antireflection film in said forming said resist mask.

Assignments (2)
CHANGE OF NAME Recorded Nov 11, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025346/0877 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2005
From: SODA, EIICHI; YABE, SACHIKO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 017150/0754 →