Semiconductor device
View Patent ↗At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well located closer to the bottom side of the p-type Si substrate than the p-type well, so as to isolate the p-type well from a bottom-side region of the p-type Si substrate. The deep n-type well includes a first deep n-type well. The deep n-type well includes a second deep n-type well located closer to the bottom side of the p-type Si substrate than the first deep n-type well, and having an n-type impurity concentration, which is different from the first deep n-type well.
1. A semiconductor device comprising:
a semiconductor substrate having a first conductivity type;
a first element region formed at an element formation surface side of said semiconductor substrate; and
a second element region formed at said element formation surface side of said semiconductor substrate;
wherein said first element region includes:
a first region having said first conductivity type,
a second region having a second conductivity type opposite to said first conductivity type, and
a third region having said second conductivity type and being formed closer to a bottom side of said semiconductor substrate that is opposite said element formation surface side than said first region is to said bottom side, so as to isolate said first region from said bottom side of said semiconductor substrate; and
said third region includes:
a second conductivity type first lower region contacting a lower face of said first region, and
a second conductivity type second lower region formed closer to the bottom side of said semiconductor substrate than said first lower region and contacting a lower surface of said first lower region, and having an impurity concentration less than said first lower region.
2. The semiconductor device according to claim 1 ,
wherein a lower face of said second lower region is joined to said semiconductor substrate.
3. The semiconductor device according to claim 1 ,
wherein an upper face of said first lower region is joined to a lower face of said second region, and
said impurity concentration of said first lower region is lower than said impurity concentration of said second lower region.
4. The semiconductor device according to claim 1 ,
wherein a plurality of said second regions is provided, and
said upper face of said first lower region is joined to said lower face of said plurality of said second regions.
5. The semiconductor device according to claim 1 ,
wherein said first element region constitutes at least a part of one of said digital circuit and said analog circuit, and
said second element region constitutes at least a part of the other of said digital circuit and said analog circuit.
6. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first element region formed at an element formation surface side of said semiconductor substrate; and
a second element region formed at said element formation surface side of said semiconductor substrate;
wherein said first element region includes:
a first region of said first conductivity type,
a second region of a second conductivity type that is opposite to said first conductivity type, and
a third region of said second conductivity type formed vertically between said semiconductor substrate and said first region, so as to isolate said first region from said semiconductor substrate; and
wherein said third region includes:
a first lower region having said second conductivity type contacting a lower surface of said first region, and
a second lower region formed between said semiconductor substrate and said first lower region and contacting a lower surface of said first lower region, and having an impurity concentration less than said first lower region.
7. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first element region formed at an element formation surface side of said semiconductor substrate; and
a second element region formed at said element formation surface side of said semiconductor substrate;
wherein said first element region includes:
a first region of said first conductivity type,
a second region of a second conductivity type that is opposite said first conductivity type, and
a third region of said second conductivity type formed directly below said first region and covering an entirety of a lower surface of said first region, so as to isolate said first region from said semiconductor substrate; and
wherein said third region includes:
a first lower region having said second conductivity type contacting a lower surface of said first region, and
a second lower region formed between said semiconductor substrate and said first lower region and contacting a lower surface of said first lower region, and having an impurity concentration less than said first lower region.