On-chip service processor
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
1. An integrated circuit comprising:
one or more logic blocks generating one or more system operation signals at one or more system operation clock rates; and
a service processor unit to perform test and debug operations of said logic blocks of said integrated circuit, further comprising:
a control unit;
a buffer memory;
an analysis engine;
a scan control unit,
a test bus interface; and
a built-in self test (BIST) engine;
wherein, in a first mode of operation, said service processor unit performs capture and analysis of system operation signals during normal system operation through said test bus interface.
2. An integrated circuit as in claim 1 , wherein, in a second mode of operation, said service processor unit performs tests on one or more of said one or more logic blocks through said test bus interface.
3. An integrated circuit as in claim 1 , the service processor unit further comprising at least one of the ports selected from the group consisting of:
a parallel I/O (PIO) port,
a serial I/O (SIO) port, and
a JTAG port;
wherein data and instructions are sent through said at least one of said ports to said service processor unit from an external diagnostics console, and result data is sent through said at least one of said ports from said service processor unit to said external diagnostics console.
4. An integrated circuit comprising:
one or more logic blocks generating one or more system operation signals at one or more system operation clock rates; and,
a service processor unit to perform test and debug operations of at least one of said logic blocks of said integrated circuit, further comprising:
a control unit;
a buffer memory;
an analysis engine; and
a system bus interface;
wherein, in a first mode of operation, said service processor unit performs capture and analysis of system operation signals during normal system operation through said system bus interface.
5. An integrated circuit as in claim 4 , wherein, in a second mode of operation, said system processor unit performs tests on one or more of said one or more logic blocks through said system bus interface.
6. An integrated circuit as in claim 4 , the service processor unit further comprising at least one of the ports selected from the group consisting of:
a parallel I/O (PIO) port,
a serial I/O (SIO) port, and
a JTAG port;
wherein data and instructions are sent through said at least one of said ports to said service processor unit from an external diagnostics console, and result data is sent through said at least one of said ports from said service processor unit to said external diagnostics console.