Semiconductor chip with post-passivation scheme formed over passivation layer
View Patent ↗The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
1. A chip comprising:
a silicon substrate;
a MOS device in or on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first contact pad exposed by a first opening in said passivation layer;
a second contact pad exposed by a second opening in said passivation layer;
a third contact pad exposed by a third opening in said passivation layer, wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads;
a patterned metal layer over said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first gold layer having a thickness between 1 and 10 micrometers over said passivation layer and over said first, second and third contact pads, and wherein said patterned metal layer comprises a metal trace over said passivation layer, and a fourth contact pad connected to said second contact pad through said metal trace, wherein the position of said fourth contact pad from a top perspective view is different from that of said second contact pad;
a first metal bump on said patterned metal layer and over said first contact pad;
a second metal bump on said fourth contact pad; and
a third metal bump on said patterned metal layer and over said third contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line, and wherein said first, second and third metal bumps all comprise a second gold layer, having more than 95 percent by weight of gold and having a height between 1 and 50 micrometers, directly on said first gold layer.
2. The chip of claim 1 further comprising a polymer layer between said patterned metal layer and said passivation layer.
3. The chip of claim 2 , wherein said polymer layer comprises polyimide.
4. The chip of claim 2 , wherein said polymer layer has a thickness between 3 and 10 micrometers.
5. The chip of claim 1 , wherein said patterned metal layer further comprises a titanium-containing layer under said first gold layer.
6. The chip of claim 5 , wherein said titanium-containing layer comprises tungsten.
7. The chip of claim 1 , wherein said first, second and third metal bumps are used to be connected to multiple fifth contact pads on a glass substrate.
8. The chip of claim 1 , wherein said first, second and third metal bumps are used to be connected to multiple fifth contact pads on a flexible substrate.
9. The chip of claim 1 , wherein said first, second and third contact pads comprise aluminum.
10. The chip of claim 1 , wherein said first, second and third contact pads comprise electroplated copper.
11. The chip of claim 1 , wherein said nitride layer has a thickness between 0.2 and 1 micrometer.
12. The chip of claim 1 , wherein said passivation layer further comprises an oxide layer under said nitride layer.
13. A chip comprising:
a silicon substrate;
a MOS device in or on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first contact pad exposed by a first opening in said passivation layer;
a second contact pad exposed by a second opening in said passivation layer;
a third contact pad exposed by a third opening in said passivation layer, wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads;
a patterned metal layer over said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first gold layer having a thickness between 1 and 10 micrometers over said passivation layer and over said first, second and third contact pads, and wherein said patterned metal layer comprises a first metal trace over said passivation layer, a fourth contact pad connected to said first contact pad through said first metal trace, wherein the position of said fourth contact pad from a top perspective view is different from that of said first contact pad, a second metal trace over said passivation layer, a fifth contact pad connected to said second contact pad through said second metal trace, wherein the position of said fifth contact pad from said top perspective view is different from that of said second contact pad, a third metal trace over said passivation layer, and a sixth contact pad connected to said third contact pad through said third metal trace, wherein the position of said sixth contact pad from said top perspective view is different from that of said third contact pad, wherein said second metal trace passes through a gap between said fourth and sixth contact pads;
a first metal bump on said fourth contact pad;
a second metal bump on said fifth contact pad; and
a third metal bump on said sixth contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line, and wherein said first, second and third metal bumps all comprise a second gold layer, having more than 95 percent by weight of gold and having a height between 1 and 50 micrometers, directly on said first gold layer.
14. The chip of claim 13 , wherein said patterned metal layer further comprises a titanium-containing layer under said first gold layer.
15. The chip of claim 14 , wherein said titanium-containing layer further comprises tungsten.
16. The chip of claim 13 , wherein said first, second and third contact pads comprise aluminum.
17. The chip of claim 13 , wherein said first, second and third contact pads comprise electroplated copper.
18. The chip of claim 13 , wherein said nitride layer has a thickness between 0.2 and 1 micrometer.
19. The chip of claim 13 further comprising a polymer layer between said patterned metal layer and said passivation layer.
20. The chip of claim 19 , wherein said polymer layer has a thickness between 3 and 10 micrometers.