Semiconductor device and testing method for semiconductor device
View Patent ↗To test a memory operation at as high speeds as high clock frequencies only with low clock frequencies. A semiconductor device according to an embodiment of the present invention includes: a clock output part; and a delay circuit, the clock output part setting a first state in accordance with an input of a first clock, setting a second state in accordance with an input of a delay clock from the delay circuit, and setting a third state in accordance with an input of a second clock, and the delay circuit delaying the first clock to output the delayed first clock as the delay clock. With this configuration, it is possible to test precharge and read/write access processings at as high operational speeds as high clock frequencies.
1. A semiconductor device, comprising:
a clock output part setting a first state in accordance with an input of a first clock, setting a second state in accordance with an input of a delay clock from a delay circuit and setting a third state in accordance with an input of a second clock; and
the delay circuit delaying the first clock to output the delayed first clock as the delay clock.
2. The semiconductor device according to claim 1 , wherein the delay circuit includes a selector switching a delay time.
3. The semiconductor device according to claim 1 , further comprising a memory circuit,
wherein the first state is a state of precharging the memory circuit, and the second state is a state of reading or writing data from or to the memory circuit.
4. The semiconductor device according to claim 2 , further comprising a memory circuit,
wherein the first state is a state of precharging the memory circuit, and the second state is a state of reading or writing data from or to the memory circuit.
5. A testing method for a semiconductor device, comprising:
setting a first state in accordance with an input of a first clock;
outputting a delay clock obtained by delaying the first clock;
setting a second state in accordance with an input of the delay clock; and
setting a third state in accordance with an input of a second clock.
6. The testing method for a semiconductor device according to claim 5 , wherein a delay time of the delay clock can be switched with a selector.
7. The testing method for a semiconductor device according to claim 5 , wherein the semiconductor device includes a memory circuit, and
the first state is a state of precharging the memory circuit, and the second state is a state of reading or writing data from or to the memory circuit.
8. The testing method for a semiconductor device according to claim 6 , wherein the semiconductor device includes a memory circuit, and
the first state is a state of precharging the memory circuit, and the second state is a state of reading or writing data from or to the memory circuit.