Methods of fabricating metal wiring in semiconductor devices
View Patent ↗Manufacturing costs may be reduced and yield may be improved when metal wiring in a semiconductor device is fabricated by a disclosed method including: sequentially forming an etch stop layer, an intermetal insulation layer, an anti-reflection coating layer, and a mask pattern on a semiconductor substrate formed with a lower structure; etching the anti-reflection coating layer using the mask pattern; forming a trench by removing the intermetal insulation layer to a predetermined depth by performing wet etching using the mask pattern; forming a via hole by removing the remaining intermetal insulation layer and the etch stop layer by dry etching them using the mask pattern; and removing the mask pattern.
1. A method of fabricating metal wiring in a semiconductor device, comprising:
sequentially forming an etch stop layer, an insulation layer, an anti-reflection coating layer, and a mask pattern on a semiconductor substrate;
dry etching the anti-reflection coating layer using the mask pattern;
wet etching the insulation layer to a depth less than a thickness of the insulation layer using the mask pattern to form a trench;
forming a via hole by removing a remaining portion of the insulation layer below the trench by dry etching using the mask pattern;
removing the mask pattern, and
filling the trench and via hole with a conductive material.
2. A method as defined in claim 1 , wherein the wet etching is performed with an etchant comprising a fluorine-containing solution.
3. A method as defined in claim 2 , wherein the fluorine-containing solution comprises buffered hydrogen fluoride (BHF).
4. The method of claim 1 , wherein the trench is formed in a shape of a bowl.
5. The method of claim 1 , wherein said insulation layer comprises an oxide.
6. The method of claim 5 , wherein said insulation layer comprises a first insulator layer and a second insulator layer different from the first insulator layer.
7. The method of claim 6 , wherein said insulation layer comprises a first insulator layer selected from the group consisting of silicon dioxide, a low dielectric constant (low-k) material, a polyarylether, and Flowfill.
8. The method of claim 7 , wherein said insulation layer comprises the low-k material and is selected from the group consisting of a fluorinated polyimide, a fluorinated silicate glass, an amorphous-fluorinated carbon, and low-k material derivatives of parylene-AF 4 and black diamond.
9. The method of claim 6 , wherein said second insulator layer comprises a silicon dioxide or a low-k material.
10. The method of claim 9 , wherein said insulation layer comprises the low-k material and is selected from the group consisting of a fluorinated polyimide, a fluorinated silicate glass, an amorphous-fluorinated carbon, and low-k material derivatives of parylene-AF 4 and black diamond.
11. The method of claim 5 , wherein said etch stop layer comprises silicon nitride.
12. The method of claim 1 , wherein said etch stop layer comprises silicon nitride.
13. The method of claim 1 , wherein forming said mask pattern comprises applying a photoresist on the anti-reflection coating layer and exposing and developing the photoresist.
14. The method of claim 1 , wherein selectively etching the anti-reflection coating layer comprises a dry etching process.
15. The method of claim 1 , wherein the dry etching process comprises reactive ion etching.
16. The method of claim 1 , wherein removing the mask pattern comprises an ashing process.
17. The method of claim 1 , further comprising forming a barrier metal layer after forming the via hole and before filling said trench and via hole with the conductive material.
18. The method of claim 1 , wherein filling said wench and via hole with a conductive material comprises chemical vapor deposition (CVD), physical vapor deposition (PVD), a combination of CVD and PVD, electroplating, electroless plating, or a combination thereof.